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Author	SHA1	Message	Date
Saji	f3584421dd	Create compiler README.md	2024-05-06 02:19:05 -05:00
annoyatron255	f1da587c47	Add LICENSE	2024-05-06 02:09:21 -05:00
annoyatron255	7747be721a	Add testcases README	2024-05-06 01:59:34 -05:00
annoyatron255	a9ee01b54e	Add model README and fix typo	2024-05-06 01:56:47 -05:00
annoyatron255	8c1fd24ad6	Add extraction README/update techmap README	2024-05-06 01:42:29 -05:00
annoyatron255	5c998f7b65	Add techmap README	2024-05-06 01:32:33 -05:00
annoyatron255	2ddce771fb	Mention restrictions on running mapper	2024-05-06 01:16:29 -05:00
annoyatron255	5cf7af7596	Fix links	2024-05-06 01:14:47 -05:00
annoyatron255	e1154144d6	Add README.md	2024-05-06 01:13:41 -05:00
annoyatron255	41c60bcab6	Add initial GAL22V10 model	2024-05-05 20:02:46 -05:00
saji	fb4ae03c91	fix 16v8 regression with tristate/registered ... Tristate can't be set on registered logic in 16V8. We add a check to skip those.	2024-05-05 17:30:11 -05:00
annoyatron255	3489b97b16	Add tiny_xor testcase and convince ABC to work right	2024-05-05 03:20:30 -05:00
saji	dcacb44cce	fix typo of script name	2024-05-05 03:05:46 -05:00
saji	f8884d4db5	fix yosys logging	2024-05-05 03:04:49 -05:00
saji	dc02482d53	fix off by one for sizing	2024-05-05 03:03:08 -05:00
saji	63b1ee41fb	make it execute the yosys command	2024-05-05 02:36:42 -05:00
annoyatron255	08aef59f79	Add shrink SOP and PCF files	2024-05-05 02:29:15 -05:00
saji	22ef300f0a	cleanup errors, looping feedback in place	2024-05-05 02:26:21 -05:00
saji	e5a1f84bf8	add unused-row assertion	2024-05-05 01:46:01 -05:00
saji	d3c498231e	reformat, only set mode for gal16v8	2024-05-05 01:41:26 -05:00
saji	336ed900f4	store cell names in cell, add sop size check and error	2024-05-05 01:22:31 -05:00
saji	cad9ce9af4	tristate case	2024-05-05 00:28:39 -05:00
annoyatron255	f296c19383	Ensure OLMC/SOP invariant with tristate	2024-05-05 00:20:18 -05:00
saji	5c5d325937	add olmc_test pcf and remove dummy SOP insertion from compiler	2024-05-04 23:48:50 -05:00
annoyatron255	49d558ed84	Fix techmap	2024-05-04 23:39:36 -05:00
annoyatron255	ec69cbde5b	Insert trivial SOPs between OLMCs	2024-05-04 23:34:44 -05:00
saji	abdaf710e6	add chip argument, untested 22v10	2024-05-04 21:41:58 -05:00
annoyatron255	1989470bc4	Add tristate to equiv script	2024-05-04 21:23:50 -05:00
annoyatron255	bc8fccaa17	Add gitignore and remove extra files	2024-05-04 20:59:57 -05:00
annoyatron255	45b86e75bb	Complete prove_equiv script and add flashing script	2024-05-04 20:55:57 -05:00
saji	7ce252b0cb	wip: fitter debug for self-feedback	2024-05-04 18:16:30 -05:00
saji	2e840d7cf4	add pcf	2024-05-04 17:47:39 -05:00
saji	e41aef8440	use patched galette, make comb olmc case work	2024-05-04 17:45:38 -05:00
saji	22f1a2a26b	fix pin ordering in SOP stuff	2024-05-04 16:55:22 -05:00
saji	2d6f0123cd	added and_gate_reg	2024-05-04 16:33:07 -05:00
saji	7b27f0f112	fix comb bug in registered	2024-05-04 16:30:08 -05:00
saji	b10e261681	mvp: and gate outputs something	2024-05-04 16:28:09 -05:00
saji	4154a18e90	partially working	2024-05-04 15:06:28 -05:00
saji	a550d84750	bugfixes, working on SOP stuff	2024-05-04 15:06:28 -05:00
annoyatron255	5ac484b1a8	Add initial Verilog model for the GAL16V8	2024-05-03 21:44:22 -05:00
saji	bb48e10488	wip: commit before refactor of graph code	2024-05-03 11:14:32 -05:00
saji	8bfcd28e0d	port mapping, inputs on OLMC outputs consume the OLMC	2024-05-02 17:39:36 -05:00
saji	2ad9a1d157	wip: newtype nodeindex	2024-05-02 16:11:24 -05:00
saji	0be535bfcb	wip: deferred OLMC mapping stuff	2024-05-02 15:49:05 -05:00
saji	62180c852f	wip: fitter	2024-05-02 12:38:57 -05:00
saji	9d2befc29b	added rust tool	2024-04-28 22:44:18 -05:00
annoyatron255	87efbe693d	Remove extra shell command	2024-04-06 00:33:41 -05:00
annoyatron255	56bee7db76	Add tristates	2024-04-04 20:39:30 -05:00
annoyatron255	2d6fe23577	Cleanup	2024-04-04 18:08:40 -05:00
annoyatron255	f565bf576d	Some edge cases cleaned up	2024-04-04 17:16:02 -05:00