Verilog Flow for the GAL16V8 and GAL22V10

annoyatron255 3489b97b16 Add tiny_xor testcase and convince ABC to work right		2024-05-05 03:20:30 -05:00
compiler	fix typo of script name	2024-05-05 03:05:46 -05:00
extractions	Add tristates	2024-04-04 20:39:30 -05:00
models	Add tristate to equiv script	2024-05-04 21:23:50 -05:00
techmaps	Ensure OLMC/SOP invariant with tristate	2024-05-05 00:20:18 -05:00
testcases	Add tiny_xor testcase and convince ABC to work right	2024-05-05 03:20:30 -05:00
.gitignore	Add gitignore and remove extra files	2024-05-04 20:59:57 -05:00
abc.script	Add OLMCs	2024-04-04 01:33:47 -05:00
cells_sim.v	Add tristates	2024-04-04 20:39:30 -05:00
flash_minipro.sh	Complete prove_equiv script and add flashing script	2024-05-04 20:55:57 -05:00
shrink_sop.tcl	Add shrink SOP and PCF files	2024-05-05 02:29:15 -05:00
synth_gal.tcl	Add tiny_xor testcase and convince ABC to work right	2024-05-05 03:20:30 -05:00