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Verilog Flow for the GAL16V8 and GAL22V10
8 commits 1 branch 0 tags 154 KiB
Rust 58.6%
Verilog 30.2%
Tcl 10.2%
Shell 1%
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testcases Add tristates 2024-04-04 20:39:30 -05:00
abc.script Add OLMCs 2024-04-04 01:33:47 -05:00
cells_sim.v Add tristates 2024-04-04 20:39:30 -05:00
synth_gal.tcl Add tristates 2024-04-04 20:39:30 -05:00