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Verilog Flow for the GAL16V8 and GAL22V10
7 commits 1 branch 0 tags 154 KiB
Rust 58.6%
Verilog 30.2%
Tcl 10.2%
Shell 1%
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annoyatron255 2d6fe23577
Cleanup
2024-04-04 18:08:40 -05:00
extractions Add OLMC on internal combinational nodes 2024-04-04 13:54:11 -05:00
techmaps Some edge cases cleaned up 2024-04-04 17:16:02 -05:00
testcases Cleanup 2024-04-04 12:02:51 -05:00
abc.script Add OLMCs 2024-04-04 01:33:47 -05:00
cells_sim.v Cleanup 2024-04-04 12:02:51 -05:00
synth_gal.tcl Cleanup 2024-04-04 18:08:40 -05:00