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Cleanup

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annoyatron255 2024-04-04 12:02:51 -05:00
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commit 8c695d0fb3
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7 changed files with 176 additions and 100 deletions
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96
cells_sim.v
View file

@ -1,76 +1,54 @@
module GAL_SOP (A, Y);
parameter WIDTH = 0;
parameter DEPTH = 0;
parameter TABLE = 0;
parameter WIDTH = 0;
parameter DEPTH = 0;
parameter TABLE = 0;
input [WIDTH-1:0] A;
output reg Y;
input [WIDTH-1:0] A;
output reg Y;
integer i, j;
reg match;
integer i, j;
reg match;
always @* begin
Y = 0;
for (i = 0; i < DEPTH; i=i+1) begin
match = 1;
for (j = 0; j < WIDTH; j=j+1) begin
if (TABLE[2*WIDTH*i + 2*j + 0] && A[j]) match = 0;
if (TABLE[2*WIDTH*i + 2*j + 1] && !A[j]) match = 0;
always @* begin
Y = 0;
for (i = 0; i < DEPTH; i=i+1) begin
match = 1;
for (j = 0; j < WIDTH; j=j+1) begin
if (TABLE[2*WIDTH*i + 2*j + 0] && A[j]) match = 0;
if (TABLE[2*WIDTH*i + 2*j + 1] && !A[j]) match = 0;
end
if (match) Y = 1;
end
if (match) Y = 1;
end
end
endmodule
/*module DFF_P (C, D, Q);
input C, D;
output reg Q;
always @ (posedge C)
Q <= D;
endmodule
module NDFF_P (C, D, Q);
input C, D;
output reg Q;
always @ (posedge C)
Q <= !D;
endmodule*/
module GAL_INPUT (A, Y);
input A;
output Y;
input A;
output Y;
assign Y = A;
assign Y = A;
endmodule
module GAL_OLMC (C, A, Y);
module GAL_OLMC (C, E, A, Y);
parameter REGISTERED = 0;
parameter INVERTED = 0;
parameter REGISTERED = 0;
parameter INVERTED = 0;
input C, E, A;
inout Y;
input C, A;
inout reg Y;
reg internal;
generate
if (REGISTERED == 1) begin
always @ (posedge C) begin
Y <= (INVERTED == 0) ? A : !A;
assign Y = E ? internal : 1'bZ;
generate
if (REGISTERED == 1) begin
always @ (posedge C) begin
internal <= (INVERTED == 0) ? A : !A;
end
end else begin
always @ (*) begin
internal <= (INVERTED == 0) ? A : !A;
end
end
end else begin
always @ (*) begin
Y <= (INVERTED == 0) ? A : !A;
end
end
endgenerate
endgenerate
endmodule

24
extractions/macrocells.v
View file

@ -1,24 +0,0 @@
module SOP_DFF (C, A, Y);
parameter WIDTH = 4;
parameter DEPTH = 0;
parameter TABLE = 0;
input C;
input [3:0] A;
output Y;
wire sop;
GAL_SOP #(
.WIDTH(WIDTH),
.DEPTH(DEPTH),
.TABLE(TABLE))
gal_sop_inst (
.A(A),
.Y(sop)
);
DFF_P dff_inst(.C(C), .D(sop), .Q(Y));
endmodule

2
synth_gal.tcl
View file

@ -62,7 +62,7 @@ techmap -map techmaps/pla.v -D PLA_MAX_PRODUCTS=10000
# Sequential OLMC
extract -map extractions/ndff.v
extract -constports -map extractions/olmc.v
techmap -map techmaps/olmc.v o:* %x o:* %d
techmap -map techmaps/olmc_seq.v
# Combinational OLMC
iopadmap -bits -outpad GAL_COMB_OUTPUT_P A:Y */t:GAL_SOP "%x:+\[Y\]" */t:GAL_SOP %d o:* %i

2
techmaps/olmc_comb.v
View file

@ -8,6 +8,7 @@ module _80_GAL_COMB_OUTPUT_P (A, Y);
.INVERTED(1'b0)
) _TECHMAP_REPLACE_ (
.C(1'bX),
.E(1'b1),
.A(A),
.Y(Y)
);
@ -24,6 +25,7 @@ module _80_NOT (A, Y);
.INVERTED(1'b1)
) _TECHMAP_REPLACE_ (
.C(1'bX),
.E(1'b1),
.A(A),
.Y(Y)
);

54
techmaps/olmc.v → techmaps/olmc_seq.v
View file

@ -9,12 +9,31 @@ module _80_REG_OUT_P (C, A, Y);
.INVERTED(1'b0)
) _TECHMAP_REPLACE_ (
.C(C),
.E(1'b1),
.A(A),
.Y(Y)
);
endgenerate
endmodule
(* techmap_celltype = "DFF_P" *)
module _80_DFF_P (C, D, Q);
input C, D;
output Q;
generate
GAL_OLMC #(
.REGISTERED(1'b1),
.INVERTED(1'b0)
) _TECHMAP_REPLACE_ (
.C(C),
.E(1'b1),
.A(D),
.Y(Q)
);
endgenerate
endmodule
(* techmap_celltype = "REG_OUT_N" *)
module _81_REG_OUT_N (C, A, Y);
input C, A;
@ -26,31 +45,34 @@ module _81_REG_OUT_N (C, A, Y);
.INVERTED(1'b1)
) _TECHMAP_REPLACE_ (
.C(C),
.E(1'b1),
.A(A),
.Y(Y)
);
endgenerate
endmodule
(* techmap_celltype = "NDFF_P" *)
module _81_NDFF_P (C, D, Q);
input C, D;
output Q;
generate
GAL_OLMC #(
.REGISTERED(1'b1),
.INVERTED(1'b1)
) _TECHMAP_REPLACE_ (
.C(C),
.E(1'b1),
.A(D),
.Y(Q)
);
endgenerate
endmodule
(* techmap_celltype = "GAL_OUTPUT" *)
module _82_GAL_OUTPUT (A);
input A;
// Delete
endmodule
(* techmap_celltype = "GAL_COMB_OUTPUT_P" *)
module _82_GAL_COMB_OUTPUT_P (A, Y);
input A, Y;
generate
GAL_OLMC #(
.REGISTERED(1'b0),
.INVERTED(1'b0)
) _TECHMAP_REPLACE_ (
.C(1'bX),
.A(A),
.Y(Y)
);
endgenerate
endmodule

83
testcases/mc14500b.v Normal file
View file

@ -0,0 +1,83 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Nobody
// Engineer: Saji Champlin
//
// Create Date: 02/06/2020 11:53:40 AM
// Design Name: MC14500B ICU
// Module Name: mc14500b
// Project Name: MC145k Computing system
// Target Devices:
// Tool Versions:
// Description:
// A dumb 1 bit computer with associated modules to allow for simple programs.
// Dependencies:
// None
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mc14500b(
input clk,
input [3:0] i_inst,
input i_data,
output reg write,
output reg jmp,
output reg rtn,
output reg flag0,
output reg flagf,
output reg o_rr,
output reg o_data
);
reg ien, oen;
reg skip;
always @(posedge clk) begin
// Reset any flags from last clock.
jmp <= 0;
rtn <= 0;
flag0 <= 0;
flagf <= 0;
write <= 0; // FIX this it's not right technically.
if (~skip) begin // skip
case(i_inst)
4'b0000 : flag0 <= 1; // NOPO
4'b0001 : o_rr <= ien & i_data; // LD
4'b0010 : o_rr <= ien & ~i_data; // LDC
4'b0011 : o_rr <= ien & (i_data & o_rr); // AND
4'b0100 : o_rr <= ien & (~i_data & o_rr); // NAND
4'b0101 : o_rr <= ien & (i_data | o_rr); // OR
4'b0110 : o_rr <= ien & (~i_data | o_rr); // NOR
4'b0111 : o_rr <= ien & (o_rr == i_data); // XNOR
4'b1000 : begin // STO
// DATA -> RR, WRITE -> 1 for a clock (if oen is allowed).
o_data <= oen & o_rr;
write <= oen;
end
4'b1001 : begin // STOC
// DATA -> ~RR, WRITE -> 1 for a clock.
o_data <= ~o_rr;
write <= oen;
end
4'b1010 : ien <= i_data;
4'b1011 : oen <= i_data;
4'b1100 : jmp <= 1;
4'b1101 : begin // RTN
rtn <= 1;
skip <= 1;
end
4'b1110 : skip <= ~o_rr;
4'b1111 : flagf <= 1;
endcase
end
else begin // reset skip flag after clocking with skip once.
skip <= 0;
end
end // neg edge
// always @(posedge clk) begin
// write <= 0;
// end
endmodule

15
testcases/olmc_test.v Normal file
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@ -0,0 +1,15 @@
module olmc_test (clk, A, B, AND, NAND, REG_AND, REG_NAND);
input clk, A, B;
output AND, NAND;
output reg REG_AND, REG_NAND;
assign AND = A && B;
assign NAND = !(A && B);
always @ (posedge clk) begin
REG_AND <= A && B;
REG_NAND <= !(A && B);
end
endmodule