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79 lines
1.1 KiB
Verilog
79 lines
1.1 KiB
Verilog
(* techmap_celltype = "REG_OUT_P" *)
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module _80_REG_OUT_P (C, A, Y);
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input C, A;
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output Y;
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generate
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GAL_OLMC #(
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.REGISTERED(1'b1),
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.INVERTED(1'b0)
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) _TECHMAP_REPLACE_ (
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.C(C),
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.E(1'b1),
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.A(A),
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.Y(Y)
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);
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endgenerate
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endmodule
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(* techmap_celltype = "DFF_P" *)
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module _80_DFF_P (C, D, Q);
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input C, D;
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output Q;
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generate
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GAL_OLMC #(
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.REGISTERED(1'b1),
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.INVERTED(1'b0)
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) _TECHMAP_REPLACE_ (
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.C(C),
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.E(1'b1),
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.A(D),
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.Y(Q)
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);
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endgenerate
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endmodule
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(* techmap_celltype = "REG_OUT_N" *)
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module _81_REG_OUT_N (C, A, Y);
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input C, A;
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output Y;
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generate
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GAL_OLMC #(
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.REGISTERED(1'b1),
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.INVERTED(1'b1)
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) _TECHMAP_REPLACE_ (
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.C(C),
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.E(1'b1),
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.A(A),
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.Y(Y)
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);
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endgenerate
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endmodule
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(* techmap_celltype = "NDFF_P" *)
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module _81_NDFF_P (C, D, Q);
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input C, D;
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output Q;
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generate
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GAL_OLMC #(
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.REGISTERED(1'b1),
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.INVERTED(1'b1)
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) _TECHMAP_REPLACE_ (
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.C(C),
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.E(1'b1),
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.A(D),
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.Y(Q)
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);
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endgenerate
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endmodule
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(* techmap_celltype = "GAL_OUTPUT" *)
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module _82_GAL_OUTPUT (A);
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input A;
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// Delete
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endmodule
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