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https://github.com/annoyatron255/yosys4gal.git
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Add initial GAL22V10 model
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annoyatron255
parent
fb4ae03c91
commit
41c60bcab6
3
models/.gitignore
vendored
3
models/.gitignore
vendored
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@ -1,4 +1,5 @@
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a.out
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dump.vcd
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GAL16V8_reg.bin
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GAL16V8_reg.hex
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GAL22V10_reg.hex
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__temp.bin
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163
models/GAL22V10_reg.v
Normal file
163
models/GAL22V10_reg.v
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@ -0,0 +1,163 @@
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`default_nettype none
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module GAL22V10_reg (
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input wire [12:0] in, // Pin {13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1}, 1 is clk
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inout wire [9:0] io // Pin {14, 15, 16, 17, 18, 19, 20, 21, 22, 23}
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);
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// Read in binary JEDEC file
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reg [7:0] jed_bin_file [0:740];
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initial $readmemh("GAL22V10_reg.hex", jed_bin_file);
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// Linearize to a fuse map
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wire [5891:0] fuses;
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genvar i, j;
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generate
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for (i = 0; i < 736; i = i + 1) begin
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for (j = 0; j < 8; j = j + 1) begin
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assign fuses[8*i + j] = jed_bin_file[i + 4][j];
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end
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end
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// Last couple bits
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for (j = 0; j < 4; j = j + 1) begin
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assign fuses[8*736 + j] = jed_bin_file[736 + 4][j];
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end
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endgenerate
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// Extract useful fuses
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wire [9:0] xor_fuses;
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assign xor_fuses = {fuses[5826], fuses[5824], fuses[5822], fuses[5820], fuses[5818],
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fuses[5816], fuses[5814], fuses[5812], fuses[5810], fuses[5808]};
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wire [9:0] reg_fuses;
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assign reg_fuses = {fuses[5827], fuses[5825], fuses[5823], fuses[5821], fuses[5819],
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fuses[5817], fuses[5815], fuses[5813], fuses[5811], fuses[5809]};
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wire [747:0] sop_fuses [0:9];
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assign sop_fuses[0] = {352'b0, fuses[439:44]};
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assign sop_fuses[1] = {264'b0, fuses[923:440]};
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assign sop_fuses[2] = {176'b0, fuses[1495:924]};
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assign sop_fuses[3] = {88'b0, fuses[2155:1496]};
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assign sop_fuses[4] = fuses[2903:2156];
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assign sop_fuses[5] = fuses[3651:2904];
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assign sop_fuses[6] = {88'b0, fuses[4311:3652]};
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assign sop_fuses[7] = {176'b0, fuses[4883:4312]};
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assign sop_fuses[8] = {264'b0, fuses[5367:4884]};
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assign sop_fuses[9] = {352'b0, fuses[5763:5368]};
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// Interleave in and feedback for SOP inputs
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wire [9:0] feedback;
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wire [21:0] interleaved;
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generate
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for (i = 0; i < 10; i = i + 1) begin
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assign interleaved[2*i +: 2] = {feedback[i], in[i]};
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end
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assign interleaved[21:20] = {in[11], in[10]};
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endgenerate
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// Generate GAL elements
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generate
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for (i = 0; i < 10; i = i + 1) begin
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wire one_sop_out, sop_out;
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// 1SOP
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sop #(
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.NUM_PRODUCTS(1),
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.NUM_INPUTS(22)
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) one_sop_inst (
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.sop_fuses(sop_fuses[i][43:0]),
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.in(interleaved),
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.out(one_sop_out)
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);
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// SOP
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sop #(
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.NUM_PRODUCTS(16),
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.NUM_INPUTS(22)
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) sop_inst (
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.sop_fuses(sop_fuses[i][747:44]),
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.in(interleaved),
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.out(sop_out)
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);
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// OLMC
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olmc olmc_inst (
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.xor_fuse(xor_fuses[i]),
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.reg_fuse(reg_fuses[i]),
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.sop(sop_out),
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.one_sop(one_sop_out),
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.clk(in[0]),
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.io(io[i]),
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.feedback(feedback[i])
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);
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end
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endgenerate
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// Simulation printing
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initial begin
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#1;
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$display("XOR: %b, REG: %b", xor_fuses, reg_fuses);
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$display("Fuses: %x", fuses);
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$display("sop0 %x", sop_fuses[0]);
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$display("sop1 %x", sop_fuses[1]);
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$display("sop2 %x", sop_fuses[2]);
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$display("sop3 %x", sop_fuses[3]);
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$display("sop4 %x", sop_fuses[4]);
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$display("sop5 %x", sop_fuses[5]);
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$display("sop6 %x", sop_fuses[6]);
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$display("sop7 %x", sop_fuses[7]);
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$display("sop8 %x", sop_fuses[8]);
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$display("sop9 %x", sop_fuses[9]);
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end
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endmodule
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module sop #(
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parameter NUM_PRODUCTS = 7,
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parameter NUM_INPUTS = 16
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)(
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input wire [2*NUM_INPUTS*NUM_PRODUCTS-1:0] sop_fuses,
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input wire [NUM_INPUTS-1:0] in,
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output reg out
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);
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integer i, j;
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reg match;
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always @ (*) begin
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out = 0;
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for (i = 0; i < NUM_PRODUCTS; i = i + 1) begin
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match = 1;
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for (j = 0; j < NUM_INPUTS; j = j + 1) begin
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if (!sop_fuses[2*NUM_INPUTS*i + 2*j + 0] && !in[j]) match = 0;
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if (!sop_fuses[2*NUM_INPUTS*i + 2*j + 1] && in[j]) match = 0;
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end
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if (match) out = 1;
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end
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end
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endmodule
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module olmc (
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input wire xor_fuse,
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input wire reg_fuse,
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input wire sop,
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input wire one_sop,
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input wire clk,
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inout wire io,
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output wire feedback
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);
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// Internal combined SOP output with optional inversion
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wire out;
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assign out = sop ^ xor_fuse;
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reg reg_out;
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always @ (posedge clk) begin
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reg_out <= out;
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end
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assign feedback = reg_fuse ? !out : !reg_out ^ xor_fuse;
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assign io = reg_fuse ? (one_sop ? !out : 1'bz) : // Combinational
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(one_sop ? !reg_out : 1'bz); // Registered
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endmodule
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30
models/GAL22V10_reg_tb.v
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30
models/GAL22V10_reg_tb.v
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@ -0,0 +1,30 @@
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module GAL22V10_reg_tb(
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output reg [12:0] in = 13'bx_xxxx_xxxx_xxx1,
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inout wire [9:0] io
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);
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GAL22V10_reg GAL22V10_reg_inst (
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.in(in),
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.io(io)
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);
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always #5 in[0] = !in[0];
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initial begin
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$dumpfile("dump.vcd");
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$dumpvars(0, GAL22V10_reg_tb);
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#3;
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in[12:1] = 12'bxxxx_xxxx_x00x;
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#10;
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in[12:1] = 12'bxxxx_xxxx_x01x;
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#10;
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in[12:1] = 12'bxxxx_xxxx_x10x;
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#10;
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in[12:1] = 12'bxxxx_xxxx_x11x;
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#10;
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in[12:1] = 12'bxxxx_xxxx_x00x;
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#10;
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$finish;
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end
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endmodule
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12
models/GAL22V10_wrapper.v
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12
models/GAL22V10_wrapper.v
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@ -0,0 +1,12 @@
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`default_nettype none
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module __wrapper (
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input wire [12:0] __in, // Pin {13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1}, 1 is clk
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inout wire [9:0] __io // Pin {14, 15, 16, 17, 18, 19, 20, 21, 22, 23}
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);
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GAL22V10_reg GAL22V10_reg_inst (
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.in(__in),
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.io(__io)
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);
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endmodule
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@ -2,7 +2,7 @@
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yosys -import
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# Parse arguments
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if { $argc < 3 } {
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if {$argc < 3} {
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puts "USAGE: $argv0 -- <JEDEC_FILE> <PCF_FILE> <VERILOG FILES> ..."
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exit
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}
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@ -11,24 +11,44 @@ set jedec_file [lindex $argv 0]
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set pcf_file [lindex $argv 1]
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set verilog_files [lrange $argv 2 end]
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# Convert JEDEC file to hex for Verilog model
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exec jedutil -convert $jedec_file GAL16V8_reg.bin
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exec xxd -ps -c 1 GAL16V8_reg.bin GAL16V8_reg.hex
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# Convert JEDEC file to bin
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exec jedutil -convert $jedec_file __temp.bin
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# Find chip being used
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set jedec_bin_size [file size __temp.bin]
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if {$jedec_bin_size == 279} {
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set chip GAL16V8
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set pin_mapping [dict create 1 "clk" 2 "in\[0\]" 3 "in\[1\]" 4 "in\[2\]" 5 "in\[3\]" 6 "in\[4\]" 7 "in\[5\]" 8 "in\[6\]" 9 "in\[7\]" 11 "oe_n" 12 "io\[7\]" 13 "io\[6\]" 14 "io\[5\]" 15 "io\[4\]" 16 "io\[3\]" 17 "io\[2\]" 18 "io\[1\]" 19 "io\[0\]"]
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} elseif {$jedec_bin_size == 741} {
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set chip GAL22V10
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set pin_mapping [dict create 1 "in\[0\]" 2 "in\[1\]" 3 "in\[2\]" 4 "in\[3\]" 5 "in\[4\]" 6 "in\[5\]" 7 "in\[6\]" 8 "in\[7\]" 9 "in\[8\]" 10 "in\[9\]" 11 "in\[10\]" 12 "in\[11\]" 13 "in\[12\]" 14 "io\[9\]" 15 "io\[8\]" 16 "io\[7\]" 17 "io\[6\]" 18 "io\[5\]" 19 "io\[4\]" 20 "io\[3\]" 21 "io\[2\]" 22 "io\[1\]" 23 "io\[0\]"]
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} else {
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puts "Error: Unknown chip for JEDEC file"
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exit
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}
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puts "Chip found to be $chip"
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# Convert binary JEDEC file to hex for Verilog
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exec xxd -ps -c 1 __temp.bin ${chip}_reg.hex
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exec rm __temp.bin
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# Read and synthesize original Verilog
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read_verilog $verilog_files
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hierarchy -auto-top
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flatten
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tribuf
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synth
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#yosys proc
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#yosys memory
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#clean -purge
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flatten
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splitnets -ports
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yosys rename -top __original
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select -module __original
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# Process PCF file and rename ports
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set used [list]
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set pin_mapping [dict create 1 "clk" 2 "in\[0\]" 3 "in\[1\]" 4 "in\[2\]" 5 "in\[3\]" 6 "in\[4\]" 7 "in\[5\]" 8 "in\[6\]" 9 "in\[7\]" 11 "oe_n" 12 "io\[7\]" 13 "io\[6\]" 14 "io\[5\]" 15 "io\[4\]" 16 "io\[3\]" 17 "io\[2\]" 18 "io\[1\]" 19 "io\[0\]"]
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set pcf_fp [open $pcf_file r]
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foreach line [split [read $pcf_fp] "\n"] {
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puts $line
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@ -45,10 +65,15 @@ select -clear
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design -stash __original
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# Read and synthesize GAL model
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read_verilog wrapper.v GAL16V8_reg.v
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flatten
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read_verilog ${chip}_wrapper.v ${chip}_reg.v
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tribuf
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synth
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#yosys proc
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#yosys memory
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#clean -purge
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flatten
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splitnets -ports
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select -module __wrapper
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@ -56,7 +81,7 @@ select -module __wrapper
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foreach pin_name [dict values $pin_mapping] {
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if {[lsearch -exact $used $pin_name] >= 0} {
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puts "$pin_name is used"
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} elseif {$pin_name == "oe_n"} {
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} elseif {$pin_name == "oe_n" && $chip == "GAL16V8"} {
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puts "$pin_name is not used"
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# Enable registered outputs if net unused
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connect -set __oe_n '0
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@ -74,4 +99,5 @@ design -copy-from __original -as __original A:top
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equiv_make __original __wrapper equiv
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tribuf -formal equiv
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equiv_induct equiv
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shell
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equiv_status -assert equiv
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@ -1,7 +1,7 @@
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set_io clk 1
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set_io A 3
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set_io B 4
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set_io AND 13
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set_io NAND 14
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set_io REG_AND 15
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set_io AND 14
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set_io NAND 15
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set_io REG_AND 17
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set_io REG_NAND 16
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