mirror of
https://github.com/annoyatron255/yosys4gal.git
synced 2024-12-22 18:52:23 +00:00
104 lines
2.6 KiB
Tcl
Executable file
104 lines
2.6 KiB
Tcl
Executable file
#!/usr/bin/env -S yosys -c
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yosys -import
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# Parse arguments
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if {$argc < 3} {
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puts "USAGE: $argv0 -- <JEDEC_FILE> <PCF_FILE> <VERILOG FILES> ..."
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exit
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}
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set jedec_file [lindex $argv 0]
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set pcf_file [lindex $argv 1]
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set verilog_files [lrange $argv 2 end]
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# Convert JEDEC file to bin
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exec jedutil -convert $jedec_file __temp.bin
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# Find chip being used
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set jedec_bin_size [file size __temp.bin]
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if {$jedec_bin_size == 279} {
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set chip GAL16V8
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set pin_mapping [dict create 1 "clk" 2 "in\[0\]" 3 "in\[1\]" 4 "in\[2\]" 5 "in\[3\]" 6 "in\[4\]" 7 "in\[5\]" 8 "in\[6\]" 9 "in\[7\]" 11 "oe_n" 12 "io\[7\]" 13 "io\[6\]" 14 "io\[5\]" 15 "io\[4\]" 16 "io\[3\]" 17 "io\[2\]" 18 "io\[1\]" 19 "io\[0\]"]
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} elseif {$jedec_bin_size == 741} {
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set chip GAL22V10
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set pin_mapping [dict create 1 "in\[0\]" 2 "in\[1\]" 3 "in\[2\]" 4 "in\[3\]" 5 "in\[4\]" 6 "in\[5\]" 7 "in\[6\]" 8 "in\[7\]" 9 "in\[8\]" 10 "in\[9\]" 11 "in\[10\]" 12 "in\[11\]" 13 "in\[12\]" 14 "io\[9\]" 15 "io\[8\]" 16 "io\[7\]" 17 "io\[6\]" 18 "io\[5\]" 19 "io\[4\]" 20 "io\[3\]" 21 "io\[2\]" 22 "io\[1\]" 23 "io\[0\]"]
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} else {
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puts "Error: Unknown chip for JEDEC file"
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exit
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}
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puts "Chip found to be $chip"
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# Convert binary JEDEC file to hex for Verilog
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exec xxd -ps -c 1 __temp.bin ${chip}_reg.hex
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exec rm __temp.bin
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# Read and synthesize original Verilog
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read_verilog $verilog_files
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hierarchy -auto-top
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tribuf
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synth
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#yosys proc
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#yosys memory
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#clean -purge
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flatten
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splitnets -ports
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yosys rename -top __original
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select -module __original
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# Process PCF file and rename ports
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set used [list]
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set pcf_fp [open $pcf_file r]
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foreach line [split [read $pcf_fp] "\n"] {
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puts $line
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if {[regexp {set_io\s+(.*)\s+([0-9]+)} $line -> net pin]} {
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# Rename nets to match GAL model
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yosys rename $net __[dict get $pin_mapping $pin]
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# Mark as used
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lappend used [dict get $pin_mapping $pin]
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}
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}
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select -clear
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design -stash __original
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# Read and synthesize GAL model
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read_verilog ${chip}_wrapper.v ${chip}_reg.v
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tribuf
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synth
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#yosys proc
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#yosys memory
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#clean -purge
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flatten
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splitnets -ports
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select -module __wrapper
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# Delete extra "unused" ports
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foreach pin_name [dict values $pin_mapping] {
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if {[lsearch -exact $used $pin_name] >= 0} {
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puts "$pin_name is used"
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} elseif {$pin_name == "oe_n" && $chip == "GAL16V8"} {
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puts "$pin_name is not used"
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# Enable registered outputs if net unused
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connect -set __oe_n '0
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delete -port __$pin_name
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} else {
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puts "$pin_name is not used"
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delete -port __$pin_name
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}
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}
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select -clear
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# Make and check equivalence circuit
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design -copy-from __original -as __original A:top
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equiv_make __original __wrapper equiv
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tribuf -formal equiv
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equiv_induct equiv
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shell
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equiv_status -assert equiv
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