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Verilog Flow for the GAL16V8 and GAL22V10
16 commits 1 branch 0 tags 154 KiB
Rust 58.6%
Verilog 30.2%
Tcl 10.2%
Shell 1%
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annoyatron255 5ac484b1a8
Add initial Verilog model for the GAL16V8
2024-05-03 21:44:22 -05:00
compiler wip: commit before refactor of graph code 2024-05-03 11:14:32 -05:00
extractions Add tristates 2024-04-04 20:39:30 -05:00
models Add initial Verilog model for the GAL16V8 2024-05-03 21:44:22 -05:00
techmaps Add tristates 2024-04-04 20:39:30 -05:00
testcases Add tristates 2024-04-04 20:39:30 -05:00
abc.script Add OLMCs 2024-04-04 01:33:47 -05:00
cells_sim.v Add tristates 2024-04-04 20:39:30 -05:00
synth_gal.tcl Remove extra shell command 2024-04-06 00:33:41 -05:00