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added rust tool
This commit is contained in:
parent
87efbe693d
commit
9d2befc29b
1
compiler/.gitignore
vendored
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1
compiler/.gitignore
vendored
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@ -0,0 +1 @@
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/target
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836
compiler/Cargo.lock
generated
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836
compiler/Cargo.lock
generated
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@ -0,0 +1,836 @@
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# This file is automatically @generated by Cargo.
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|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "5eee091590e89cc02ad514ffe3ead9eb6b660aedca2183455434b93546371a03"
|
||||
|
||||
[[package]]
|
||||
name = "windows_x86_64_gnullvm"
|
||||
version = "0.52.4"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "77ca79f2451b49fa9e2af39f0747fe999fcda4f5e241b2898624dca97a1f2177"
|
||||
|
||||
[[package]]
|
||||
name = "windows_x86_64_msvc"
|
||||
version = "0.52.4"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "32b752e52a2da0ddfbdbcc6fceadfeede4c939ed16d13e648833a61dfb611ed8"
|
||||
23
compiler/Cargo.toml
Normal file
23
compiler/Cargo.toml
Normal file
|
|
@ -0,0 +1,23 @@
|
|||
[package]
|
||||
name = "ver2gal"
|
||||
version = "0.1.0"
|
||||
edition = "2021"
|
||||
|
||||
# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
|
||||
|
||||
[dependencies]
|
||||
anyhow = "1.0.81"
|
||||
clap = { version = "4.5.4", features = ["derive"] }
|
||||
galette = "0.3.0"
|
||||
log = "0.4.21"
|
||||
regex = "1.10.4"
|
||||
serde = { version = "1.0.197", features = ["derive"] }
|
||||
serde_json = "1.0.115"
|
||||
serde_with = { version = "3.7.0", features = ["json"] }
|
||||
|
||||
|
||||
[lib]
|
||||
name = "ver2gal"
|
||||
|
||||
[[bin]]
|
||||
name = "ver2gal"
|
||||
2
compiler/src/lib.rs
Normal file
2
compiler/src/lib.rs
Normal file
|
|
@ -0,0 +1,2 @@
|
|||
pub mod yosys_parser;
|
||||
pub mod pcf;
|
||||
52
compiler/src/main.rs
Normal file
52
compiler/src/main.rs
Normal file
|
|
@ -0,0 +1,52 @@
|
|||
pub mod pcf;
|
||||
pub mod yosys_parser;
|
||||
|
||||
use clap::{Parser, Subcommand, Args};
|
||||
use crate::yosys_parser::{YosysDoc, Graph};
|
||||
use anyhow::{bail, Result};
|
||||
use serde_json::from_slice;
|
||||
use std::path::PathBuf;
|
||||
use std::fs;
|
||||
|
||||
#[derive(Parser)]
|
||||
struct Cli {
|
||||
#[command(subcommand)]
|
||||
command: Commands,
|
||||
}
|
||||
|
||||
#[derive(Subcommand)]
|
||||
enum Commands {
|
||||
/// Validate a yosys netlist JSON file.
|
||||
Validate(ValidateArgs),
|
||||
}
|
||||
|
||||
#[derive(Args)]
|
||||
struct ValidateArgs {
|
||||
#[arg(required = true, value_hint = clap::ValueHint::DirPath)]
|
||||
file: PathBuf,
|
||||
}
|
||||
|
||||
|
||||
fn validate(v: ValidateArgs) -> Result<()>{
|
||||
let f = fs::read(v.file)?;
|
||||
|
||||
let data: YosysDoc = from_slice(f.as_slice())?;
|
||||
|
||||
let g = Graph::from(data);
|
||||
let res = g.validate().map_err(|x| x.to_string());
|
||||
if let Err(e) = res {
|
||||
bail!(e);
|
||||
}
|
||||
println!("Validation Complete!");
|
||||
println!("Stats:");
|
||||
println!("Nodes: {}", g.nodelist.len());
|
||||
println!("Edges: {}", g.adjlist.len());
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn main() -> Result<()>{
|
||||
let args = Cli::parse();
|
||||
match args.command {
|
||||
Commands::Validate(v) => validate(v),
|
||||
}
|
||||
}
|
||||
67
compiler/src/pcf.rs
Normal file
67
compiler/src/pcf.rs
Normal file
|
|
@ -0,0 +1,67 @@
|
|||
use regex::Regex;
|
||||
use std::collections::HashMap;
|
||||
|
||||
pub struct PcfFile {
|
||||
map: HashMap<String, u32>,
|
||||
}
|
||||
|
||||
pub fn parse_pcf(input: &str) -> PcfFile {
|
||||
let mut pcf = HashMap::new();
|
||||
let re = Regex::new(r"(?m)^set_io (\S+) (\d+)$").unwrap();
|
||||
// we run a captures on it.
|
||||
for (_, [name, pin]) in re.captures_iter(input).map(|c| c.extract()) {
|
||||
if pcf.contains_key(name) {
|
||||
panic!("name collision in pcf file");
|
||||
}
|
||||
let num: u32 = str::parse(pin).unwrap();
|
||||
pcf.insert(name.to_string(), num);
|
||||
}
|
||||
PcfFile { map: pcf }
|
||||
}
|
||||
|
||||
impl PcfFile {
|
||||
pub fn pin(&self, name: &str) -> Option<u32> {
|
||||
self.map.get(name).cloned()
|
||||
}
|
||||
pub fn pinvec(&self, name: &str, index: usize) -> Option<u32> {
|
||||
// construct a name of the form <name>[<index>]
|
||||
let realname = format!("{name}[{index}]");
|
||||
self.map.get(&realname).cloned()
|
||||
}
|
||||
}
|
||||
|
||||
#[cfg(test)]
|
||||
mod tests {
|
||||
use super::*;
|
||||
#[test]
|
||||
fn test_basic() {
|
||||
let test_str = "set_io pinName 1";
|
||||
let name_expected = "pinName";
|
||||
let pin_expected = 1;
|
||||
let f = parse_pcf(test_str);
|
||||
assert_eq!(f.pin(name_expected), Some(pin_expected));
|
||||
assert_eq!(f.pin("invalid"), None);
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn test_pins() {
|
||||
let test = "
|
||||
set_io scalar 1
|
||||
set_io vec[0] 2
|
||||
set_io vec[1] 3";
|
||||
let f = parse_pcf(test);
|
||||
assert_eq!(f.pin("scalar"), Some(1));
|
||||
assert_eq!(f.pinvec("vec", 0), Some(2));
|
||||
assert_eq!(f.pinvec("vec", 1), Some(3));
|
||||
assert_eq!(f.pinvec("vec", 2), None);
|
||||
}
|
||||
|
||||
#[test]
|
||||
#[should_panic]
|
||||
fn test_name_collision() {
|
||||
let test = "
|
||||
set_io scalar 1
|
||||
set_io scalar 2";
|
||||
parse_pcf(test);
|
||||
}
|
||||
}
|
||||
511
compiler/src/yosys_parser.rs
Normal file
511
compiler/src/yosys_parser.rs
Normal file
|
|
@ -0,0 +1,511 @@
|
|||
use crate::pcf::PcfFile;
|
||||
use galette::gal::Pin;
|
||||
use log::error;
|
||||
use log::info;
|
||||
use serde::{de::Error, Deserialize, Deserializer, Serialize};
|
||||
use serde_with::{serde_as, BoolFromInt};
|
||||
use std::collections::hash_map::Iter;
|
||||
use std::collections::HashMap;
|
||||
use std::str;
|
||||
|
||||
#[derive(Debug, Serialize, Clone, Deserialize, Hash, PartialEq, Eq, PartialOrd, Ord)]
|
||||
pub enum Net {
|
||||
#[serde(rename = "x")]
|
||||
NotConnected,
|
||||
#[serde(rename = "1")]
|
||||
LiteralOne,
|
||||
#[serde(rename = "0")]
|
||||
LiteralZero,
|
||||
#[serde(untagged)]
|
||||
N(u32),
|
||||
}
|
||||
|
||||
/// The GAL_INPUT marks an external ipnut
|
||||
#[derive(Clone, Debug, Serialize, Deserialize, PartialEq)]
|
||||
pub struct GalInput {
|
||||
pub connections: HashMap<String, Vec<Net>>,
|
||||
}
|
||||
|
||||
// Custom deserializer for the strange string of binary
|
||||
// for some reason the json outputs 00000000000111 for some numbers.
|
||||
// this converts them back into binary.
|
||||
fn from_binstr<'de, D>(deserializer: D) -> Result<u32, D::Error>
|
||||
where
|
||||
D: Deserializer<'de>,
|
||||
{
|
||||
let s = String::deserialize(deserializer)?;
|
||||
u32::from_str_radix(s.as_str(), 2).map_err(D::Error::custom)
|
||||
}
|
||||
fn bool_from_binstr<'de, D>(deserializer: D) -> Result<bool, D::Error>
|
||||
where
|
||||
D: Deserializer<'de>,
|
||||
{
|
||||
let s = String::deserialize(deserializer)?;
|
||||
let val = u32::from_str_radix(s.as_str(), 2).map_err(D::Error::custom)?;
|
||||
Ok(val == 1)
|
||||
}
|
||||
|
||||
#[derive(Clone, Debug, Serialize, Deserialize, PartialEq)]
|
||||
#[serde(rename_all = "UPPERCASE")]
|
||||
pub struct GalSopParameters {
|
||||
#[serde(deserialize_with = "from_binstr")]
|
||||
pub depth: u32,
|
||||
pub table: String,
|
||||
#[serde(deserialize_with = "from_binstr")]
|
||||
pub width: u32,
|
||||
}
|
||||
|
||||
#[derive(Clone, Debug, Serialize, Deserialize, PartialEq)]
|
||||
pub struct GalSop {
|
||||
pub connections: HashMap<String, Vec<Net>>,
|
||||
pub parameters: GalSopParameters,
|
||||
}
|
||||
|
||||
#[serde_as]
|
||||
#[derive(Clone, Debug, Serialize, Deserialize, PartialEq)]
|
||||
#[serde(rename_all = "UPPERCASE")]
|
||||
pub struct GALOLMCParameters {
|
||||
#[serde(deserialize_with = "bool_from_binstr")]
|
||||
inverted: bool,
|
||||
#[serde(deserialize_with = "bool_from_binstr")]
|
||||
registered: bool,
|
||||
}
|
||||
|
||||
#[derive(Clone, Debug, Serialize, Deserialize, PartialEq)]
|
||||
pub struct GalOLMC {
|
||||
pub parameters: GALOLMCParameters,
|
||||
pub connections: HashMap<String, Vec<Net>>,
|
||||
}
|
||||
|
||||
#[derive(Clone, Debug, Serialize, Deserialize)]
|
||||
#[serde(deny_unknown_fields)]
|
||||
#[serde(tag = "type")]
|
||||
pub enum YosysCell {
|
||||
#[serde(rename = "GAL_SOP", alias = "GAL_1SOP")]
|
||||
Sop(GalSop),
|
||||
#[serde(rename = "GAL_INPUT")]
|
||||
Input(GalInput),
|
||||
#[serde(rename = "GAL_OLMC")]
|
||||
OLMC(GalOLMC),
|
||||
}
|
||||
|
||||
#[serde_as]
|
||||
#[derive(Clone, Debug, Serialize, Deserialize)]
|
||||
pub struct ModPort {
|
||||
pub bits: Vec<Net>,
|
||||
#[serde(default)]
|
||||
#[serde_as(as = "BoolFromInt")]
|
||||
pub upto: bool,
|
||||
}
|
||||
|
||||
#[derive(Clone, Debug, Serialize, Deserialize)]
|
||||
#[serde(rename_all = "lowercase", tag = "direction")]
|
||||
pub enum Port {
|
||||
Input(ModPort),
|
||||
Output(ModPort),
|
||||
InOut(ModPort),
|
||||
}
|
||||
|
||||
#[derive(Clone, Debug, Serialize, Deserialize)]
|
||||
pub struct Module {
|
||||
pub ports: HashMap<String, Port>,
|
||||
pub cells: HashMap<String, YosysCell>,
|
||||
}
|
||||
#[derive(Clone, Debug, Serialize, Deserialize)]
|
||||
pub struct YosysDoc {
|
||||
pub creator: String,
|
||||
pub modules: HashMap<String, Module>,
|
||||
}
|
||||
|
||||
impl GalSop {
|
||||
// extract the logic table using the parameters.
|
||||
// pub fn parse_table(self) -> Vec<Vec<Pin>> {
|
||||
// // get the list of inputs which is a Vec<u32>
|
||||
// let table = self.parameters.table.as_bytes();
|
||||
//
|
||||
// // split into products
|
||||
// let product_count = self.parameters.depth;
|
||||
// let product_size = self.parameters.width;
|
||||
// // we need to have enough elements.
|
||||
// assert!(table.len() == (product_count * product_size * 2) as usize);
|
||||
//
|
||||
// let chunksize = product_size * 2;
|
||||
//
|
||||
// table
|
||||
// .chunks(chunksize as usize)
|
||||
// .map(|prod| {
|
||||
// let mut term = Vec::new();
|
||||
// for i in 0..product_size {
|
||||
// let i = i as usize;
|
||||
// let pin_num = self.connections.inputs.get(i).unwrap(); // this should never panic.
|
||||
// let pin = table_seg_to_pin(pin_num, &prod[2 * i..2 * i + 1]);
|
||||
// if let Some(p) = pin {
|
||||
// term.push(p);
|
||||
// }
|
||||
// }
|
||||
// // now that we've accumulated all of the products, add it to the products list.
|
||||
// term
|
||||
// })
|
||||
// .collect()
|
||||
// }
|
||||
}
|
||||
|
||||
// table_seg_to_pin reads the small chunk for a specific input to a
|
||||
// sop and creates a gal pin for it.
|
||||
fn table_seg_to_pin(num: &Net, seg: &[u8]) -> Option<Pin> {
|
||||
let Net::N(p) = num else {
|
||||
todo!("specials");
|
||||
};
|
||||
let pin_num: usize = *p as usize;
|
||||
// convert to string for dumb reasons.
|
||||
match str::from_utf8(seg).unwrap() {
|
||||
"01" => Some(Pin {
|
||||
pin: pin_num,
|
||||
neg: true,
|
||||
}), // negated
|
||||
"10" => Some(Pin {
|
||||
pin: pin_num,
|
||||
neg: false,
|
||||
}), // normal
|
||||
_ => None,
|
||||
}
|
||||
}
|
||||
|
||||
/* constraint mapping pipeline
|
||||
* w
|
||||
* take yosys document -> look at top-level module ports
|
||||
* use constraints pcf file to map. This creates a HashMap<Net, u32> for mapping nets to pins.
|
||||
* only do this for *ports*, not cells. now we have a net->pin map, where we know that there's
|
||||
* hits.
|
||||
*/
|
||||
|
||||
#[derive(Debug, Clone, PartialEq, Eq, PartialOrd)]
|
||||
pub enum PortDirection {
|
||||
Input,
|
||||
Output,
|
||||
Inout,
|
||||
}
|
||||
/// NamedPort is our internal representation of a port.
|
||||
#[derive(Debug, Clone, PartialEq, PartialOrd)]
|
||||
pub struct NamedPort {
|
||||
name: String,
|
||||
net: Net,
|
||||
direction: PortDirection,
|
||||
}
|
||||
|
||||
use std::cmp::Ordering;
|
||||
impl NamedPort {
|
||||
fn new(name: &str, net: &Net, dir: &PortDirection) -> Self {
|
||||
NamedPort {
|
||||
name: name.to_owned(),
|
||||
net: net.clone(),
|
||||
direction: dir.clone(),
|
||||
}
|
||||
}
|
||||
|
||||
/// Takes a module port, and splits into N NamedPorts, where the name
|
||||
/// is converted to match the pcf format <name>[index] if there is more than
|
||||
/// one bit in the port
|
||||
fn new_split(base_name: &str, port: ModPort, dir: PortDirection) -> Vec<NamedPort> {
|
||||
match port.bits.len().cmp(&1) {
|
||||
Ordering::Greater => port
|
||||
.bits
|
||||
.iter()
|
||||
.enumerate()
|
||||
.map(|(idx, n)| NamedPort::new(&format!("{base_name}[{idx}]"), n, &dir))
|
||||
.collect(),
|
||||
Ordering::Equal => {
|
||||
vec![NamedPort::new(base_name, &port.bits[0], &dir)]
|
||||
}
|
||||
_ => panic!("no bits on this port!"),
|
||||
}
|
||||
}
|
||||
/// Retrieves the port mapping for this port, given a PCF file.
|
||||
pub fn lookup(&self, pcf: &PcfFile) -> u32 {
|
||||
//NOTE: since NamedPort is exactly (1) pin, we always use the pin case.
|
||||
// When constructing, if we have a port with multiple bits, we split it (see `new_split`)
|
||||
pcf.pin(&self.name).expect("missing constraint")
|
||||
}
|
||||
}
|
||||
|
||||
#[derive(Debug, Clone)]
|
||||
pub struct NetAdjPair {
|
||||
net: Net,
|
||||
idx1: usize,
|
||||
port1: String,
|
||||
port2: String,
|
||||
idx2: usize,
|
||||
}
|
||||
|
||||
impl PartialEq for NetAdjPair {
|
||||
// equality is non-directional, so we have to manually override.
|
||||
//
|
||||
fn eq(&self, other: &Self) -> bool {
|
||||
if self.net != other.net {
|
||||
return false;
|
||||
}
|
||||
// we know the nets are the same
|
||||
if self.port1 == other.port1
|
||||
&& self.port2 == other.port2
|
||||
&& self.idx1 == other.idx1
|
||||
&& self.idx2 == other.idx2
|
||||
{
|
||||
return true;
|
||||
}
|
||||
// the same, but the direction is backwards. for our intents this is fine.
|
||||
if self.port1 == other.port1
|
||||
&& self.port2 == other.port1
|
||||
&& self.idx1 == other.idx2
|
||||
&& self.idx2 == other.idx1
|
||||
{
|
||||
return true;
|
||||
}
|
||||
false
|
||||
}
|
||||
}
|
||||
|
||||
impl Eq for NetAdjPair {}
|
||||
|
||||
impl NetAdjPair {
|
||||
fn uses_net(&self, net: &Net) -> bool {
|
||||
net == &self.net
|
||||
}
|
||||
fn uses_nodeport(&self, idx: usize, port: &str) -> bool {
|
||||
self.idx1 == idx && self.port1 == port || self.idx2 == idx && self.port2 == port
|
||||
}
|
||||
}
|
||||
|
||||
/// A Node is an entry in our graph. A node has inputs and outputs.
|
||||
#[derive(Debug, PartialEq, Clone)]
|
||||
pub enum Node {
|
||||
Input(GalInput),
|
||||
Sop(GalSop),
|
||||
Olmc(GalOLMC),
|
||||
}
|
||||
|
||||
impl Node {
|
||||
/* These functions are a little odd. We invert the input/output bits. CHIP inputs, are viewed
|
||||
* as outputs internally, likewise we view the outputs of the chip as inputs (to be driven
|
||||
* internally. So get_outputs returns values on input_cells, since those are driven already.
|
||||
* Likewise we reverse this for get_inputs, since the chip's outputs are our inputs.
|
||||
*/
|
||||
// fn get_outputs(&self) -> Vec<Net> {
|
||||
// match self {
|
||||
// Self::Input(i) => i.connections.output.to_vec(),
|
||||
// Self::Sop(s) => s.connections.output.to_vec(),
|
||||
// Self::Olmc(o) => o.connections.get("Y").expect("Y outpu").to_vec(),
|
||||
// }
|
||||
// }
|
||||
// fn get_inputs(&self) -> Vec<Net> {
|
||||
// match self {
|
||||
// Self::Input(gi) => gi.connections.input.to_vec(),
|
||||
// Self::Sop(gs) => gs.connections.inputs.to_vec(),
|
||||
// Self::Olmc(go) => go.connections.input.to_vec(),
|
||||
// }
|
||||
// }
|
||||
fn get_ports(&self) -> Iter<'_, String, Vec<Net>> {
|
||||
match self {
|
||||
Self::Olmc(ol) => ol.connections.iter(),
|
||||
Self::Input(i) => i.connections.iter(),
|
||||
Self::Sop(s) => s.connections.iter(),
|
||||
}
|
||||
}
|
||||
fn port_for_net(&self, net: &Net) -> Option<String> {
|
||||
for (port, nets) in self.get_ports() {
|
||||
if nets.contains(net) {
|
||||
return Some(port.to_string());
|
||||
}
|
||||
}
|
||||
None
|
||||
}
|
||||
fn get_nets(&self) -> Vec<Net> {
|
||||
self.get_ports()
|
||||
.flat_map(|(_, nets)| nets.clone())
|
||||
.collect()
|
||||
}
|
||||
}
|
||||
|
||||
#[derive(Default, Debug)]
|
||||
pub struct Graph {
|
||||
pub nodelist: Vec<Node>,
|
||||
pub adjlist: Vec<NetAdjPair>,
|
||||
pub ports: Vec<NamedPort>,
|
||||
}
|
||||
|
||||
// For each node, for each port, for each net
|
||||
// find all other nodes that have this net.
|
||||
|
||||
impl Graph {
|
||||
/// re-generate the adjacency set for this graph.
|
||||
pub fn generate_adjacency(&mut self) {
|
||||
self.adjlist.clear();
|
||||
for (idx1, node1) in self.nodelist.iter().enumerate() {
|
||||
for net in node1.get_nets() {
|
||||
if !matches!(net, Net::N(_)) {
|
||||
info!("skipping global nets");
|
||||
continue;
|
||||
}
|
||||
let connected_nodes: Vec<_> = self
|
||||
.nodelist
|
||||
.iter()
|
||||
.enumerate()
|
||||
.filter(|&(idx2, node2)| {
|
||||
if idx1 == idx2 {
|
||||
return false;
|
||||
}
|
||||
node2.get_nets().contains(&net)
|
||||
})
|
||||
.collect();
|
||||
|
||||
for (idx2, node2) in connected_nodes {
|
||||
// get the port for node1
|
||||
let node1_port = node1.port_for_net(&net).expect("how");
|
||||
let node2_port = node2.port_for_net(&net).expect("how");
|
||||
let adj = NetAdjPair {
|
||||
net: net.clone(),
|
||||
idx1,
|
||||
idx2,
|
||||
port1: node1_port,
|
||||
port2: node2_port,
|
||||
};
|
||||
if !self.adjlist.contains(&adj) {
|
||||
// if this fails, it means that the opposing pair is already present.
|
||||
self.adjlist.push(adj);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
/// Find all nodes that are attached to this net in any way.
|
||||
/// Note that this is an expensive operation since it can't currently use the adjlist.
|
||||
pub fn find_nodes(&self, net: &Net) -> Vec<usize> {
|
||||
let mut res = Vec::new();
|
||||
for (idx, node) in self.nodelist.iter().enumerate() {
|
||||
if node.get_nets().contains(net) {
|
||||
res.push(idx);
|
||||
}
|
||||
}
|
||||
res
|
||||
}
|
||||
/// find the port that uses the current net, if any
|
||||
fn find_port(&self, net: &Net) -> Option<&NamedPort> {
|
||||
self.ports.iter().find(|p| p.net == *net)
|
||||
}
|
||||
|
||||
/// Validate that the graph has valid invariants.
|
||||
/// This function does not guarantee a mapping, but it does mean that the output produced
|
||||
/// by the yosys script is what we expected. Mainly a tool for debugging the Yosys outputs.
|
||||
pub fn validate(&self) -> Result<(), &str> {
|
||||
info!("Checking OLMC blocks");
|
||||
let all_olmc = self.nodelist.iter().filter_map(|node| match node {
|
||||
Node::Olmc(o) => Some(o),
|
||||
_ => None,
|
||||
});
|
||||
|
||||
let olmc_clock = all_olmc.filter_map(|o| o.connections.get("C"));
|
||||
let test = olmc_clock.clone().all(|v| v.len() == 1);
|
||||
if !test {
|
||||
return Err("OLMC has more than one clock input!");
|
||||
}
|
||||
// assert that all olmc C nets are either not connected or to a net
|
||||
let test = olmc_clock
|
||||
.clone()
|
||||
.flatten()
|
||||
.all(|net| matches!(net, Net::NotConnected) || matches!(net, Net::N(_)));
|
||||
if !test {
|
||||
return Err("invalid clock pin");
|
||||
}
|
||||
// for the ones connected to a net, extract the net nubmer and Vec it.
|
||||
let olmc_clocked: Vec<u32> = olmc_clock
|
||||
.clone()
|
||||
.flatten()
|
||||
.filter_map(|net| match net {
|
||||
Net::N(x) => Some(*x),
|
||||
_ => None,
|
||||
})
|
||||
.collect();
|
||||
let test = olmc_clocked.windows(2).all(|w| w[0] == w[1]);
|
||||
if !test {
|
||||
return Err("clock pin is not shared amongst all OLMCs");
|
||||
}
|
||||
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
|
||||
const TECHMAP_NAMES: [&str; 5] = ["DFF_P", "GAL_INPUT", "GAL_SOP", "GAL_OLMC", "GAL_1SOP"];
|
||||
|
||||
impl From<YosysDoc> for Graph {
|
||||
fn from(value: YosysDoc) -> Self {
|
||||
let mut g = Graph::default();
|
||||
for (mod_name, module) in value.modules {
|
||||
info!("Processing module {}", mod_name);
|
||||
if TECHMAP_NAMES.contains(&mod_name.as_str()) {
|
||||
info!("Skipping module as it is a techmap module");
|
||||
continue;
|
||||
}
|
||||
for (cell_name, cell) in module.cells {
|
||||
info!("Processing cell {}", cell_name);
|
||||
let newcell = match cell {
|
||||
YosysCell::Input(d) => Node::Input(d),
|
||||
YosysCell::Sop(s) => Node::Sop(s),
|
||||
YosysCell::OLMC(n) => Node::Olmc(n),
|
||||
};
|
||||
g.nodelist.push(newcell);
|
||||
}
|
||||
for (port_name, port) in module.ports {
|
||||
info!("Processing port {}", port_name);
|
||||
let new_ports: Vec<NamedPort> = match port {
|
||||
Port::Output(o) => NamedPort::new_split(&port_name, o, PortDirection::Output),
|
||||
Port::Input(i) => NamedPort::new_split(&port_name, i, PortDirection::Input),
|
||||
Port::InOut(io) => NamedPort::new_split(&port_name, io, PortDirection::Inout),
|
||||
};
|
||||
g.ports.extend(new_ports);
|
||||
}
|
||||
}
|
||||
g.generate_adjacency();
|
||||
g
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* This graph is too general as it stands. we cannot map individual input pins
|
||||
* like we can with our output pins. Also, i have no way of finding a specific
|
||||
* node in the graph.
|
||||
*/
|
||||
|
||||
#[cfg(test)]
|
||||
mod tests {
|
||||
use super::*;
|
||||
use anyhow::Result;
|
||||
use serde_json::from_str;
|
||||
|
||||
#[test]
|
||||
fn test_netspecial_n() -> Result<()> {
|
||||
let netstring = "23";
|
||||
let data: Net = from_str(netstring)?;
|
||||
assert_eq!(data, Net::N(23));
|
||||
Ok(())
|
||||
}
|
||||
#[test]
|
||||
fn test_netspecial_x() -> Result<()> {
|
||||
let netstring = "\"x\"";
|
||||
let data: Net = from_str(netstring)?;
|
||||
assert_eq!(data, Net::NotConnected);
|
||||
Ok(())
|
||||
}
|
||||
#[test]
|
||||
fn test_netspecial_zero() -> Result<()> {
|
||||
let netstring = "[\"0\"]";
|
||||
let data: Vec<Net> = from_str(netstring)?;
|
||||
assert_eq!(data[0], Net::LiteralZero);
|
||||
Ok(())
|
||||
}
|
||||
#[test]
|
||||
fn test_netspecial_one() -> Result<()> {
|
||||
let netstring = "\"1\"";
|
||||
let data: Net = from_str(netstring)?;
|
||||
assert_eq!(data, Net::LiteralOne);
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
514
compiler/testcases/json/synth_olmc_test.json
Normal file
514
compiler/testcases/json/synth_olmc_test.json
Normal file
|
|
@ -0,0 +1,514 @@
|
|||
{
|
||||
"creator": "Yosys 0.38 (git sha1 543faed9c, gcc 13.2.1 -march=x86-64 -mtune=generic -O2 -fno-plt -fexceptions -fstack-clash-protection -fcf-protection -ffile-prefix-map=/build/yosys/src=/usr/src/debug/yosys -fPIC -Os)",
|
||||
"modules": {
|
||||
"DFF_P": {
|
||||
"attributes": {
|
||||
"blackbox": "00000000000000000000000000000001"
|
||||
},
|
||||
"ports": {
|
||||
"C": {
|
||||
"direction": "input",
|
||||
"bits": [ 2 ]
|
||||
},
|
||||
"D": {
|
||||
"direction": "input",
|
||||
"bits": [ 3 ]
|
||||
},
|
||||
"Q": {
|
||||
"direction": "output",
|
||||
"bits": [ 4 ]
|
||||
}
|
||||
},
|
||||
"cells": {
|
||||
},
|
||||
"netnames": {
|
||||
"C": {
|
||||
"hide_name": 0,
|
||||
"bits": [ 2 ],
|
||||
"attributes": {
|
||||
}
|
||||
},
|
||||
"D": {
|
||||
"hide_name": 0,
|
||||
"bits": [ 3 ],
|
||||
"attributes": {
|
||||
}
|
||||
},
|
||||
"Q": {
|
||||
"hide_name": 0,
|
||||
"bits": [ 4 ],
|
||||
"attributes": {
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"GAL_1SOP": {
|
||||
"attributes": {
|
||||
"dynports": "00000000000000000000000000000001",
|
||||
"blackbox": "00000000000000000000000000000001",
|
||||
"cells_not_processed": "00000000000000000000000000000001",
|
||||
"src": "cells_sim.v:25.1-47.10"
|
||||
},
|
||||
"parameter_default_values": {
|
||||
"DEPTH": "00000000000000000000000000000000",
|
||||
"TABLE": "00000000000000000000000000000000",
|
||||
"WIDTH": "00000000000000000000000000000000"
|
||||
},
|
||||
"ports": {
|
||||
"A": {
|
||||
"direction": "input",
|
||||
"offset": -1,
|
||||
"upto": 1,
|
||||
"bits": [ 2, 3 ]
|
||||
},
|
||||
"Y": {
|
||||
"direction": "output",
|
||||
"bits": [ 4 ]
|
||||
}
|
||||
},
|
||||
"cells": {
|
||||
},
|
||||
"netnames": {
|
||||
"A": {
|
||||
"hide_name": 0,
|
||||
"bits": [ 2, 3 ],
|
||||
"offset": -1,
|
||||
"upto": 1,
|
||||
"attributes": {
|
||||
"src": "cells_sim.v:30.20-30.21"
|
||||
}
|
||||
},
|
||||
"Y": {
|
||||
"hide_name": 0,
|
||||
"bits": [ 4 ],
|
||||
"attributes": {
|
||||
"src": "cells_sim.v:31.13-31.14"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"GAL_INPUT": {
|
||||
"attributes": {
|
||||
"blackbox": "00000000000000000000000000000001",
|
||||
"cells_not_processed": "00000000000000000000000000000001",
|
||||
"src": "cells_sim.v:49.1-54.10"
|
||||
},
|
||||
"ports": {
|
||||
"A": {
|
||||
"direction": "input",
|
||||
"bits": [ 2 ]
|
||||
},
|
||||
"Y": {
|
||||
"direction": "output",
|
||||
"bits": [ 3 ]
|
||||
}
|
||||
},
|
||||
"cells": {
|
||||
},
|
||||
"netnames": {
|
||||
"A": {
|
||||
"hide_name": 0,
|
||||
"bits": [ 2 ],
|
||||
"attributes": {
|
||||
"src": "cells_sim.v:50.8-50.9"
|
||||
}
|
||||
},
|
||||
"Y": {
|
||||
"hide_name": 0,
|
||||
"bits": [ 3 ],
|
||||
"attributes": {
|
||||
"src": "cells_sim.v:51.9-51.10"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"GAL_OLMC": {
|
||||
"attributes": {
|
||||
"blackbox": "00000000000000000000000000000001",
|
||||
"cells_not_processed": "00000000000000000000000000000001",
|
||||
"src": "cells_sim.v:56.1-78.10"
|
||||
},
|
||||
"parameter_default_values": {
|
||||
"INVERTED": "00000000000000000000000000000000",
|
||||
"REGISTERED": "00000000000000000000000000000000"
|
||||
},
|
||||
"ports": {
|
||||
"C": {
|
||||
"direction": "input",
|
||||
"bits": [ 2 ]
|
||||
},
|
||||
"E": {
|
||||
"direction": "input",
|
||||
"bits": [ 3 ]
|
||||
},
|
||||
"A": {
|
||||
"direction": "input",
|
||||
"bits": [ 4 ]
|
||||
},
|
||||
"Y": {
|
||||
"direction": "inout",
|
||||
"bits": [ 5 ]
|
||||
}
|
||||
},
|
||||
"cells": {
|
||||
},
|
||||
"netnames": {
|
||||
"A": {
|
||||
"hide_name": 0,
|
||||
"bits": [ 4 ],
|
||||
"attributes": {
|
||||
"src": "cells_sim.v:60.14-60.15"
|
||||
}
|
||||
},
|
||||
"C": {
|
||||
"hide_name": 0,
|
||||
"bits": [ 2 ],
|
||||
"attributes": {
|
||||
"src": "cells_sim.v:60.8-60.9"
|
||||
}
|
||||
},
|
||||
"E": {
|
||||
"hide_name": 0,
|
||||
"bits": [ 3 ],
|
||||
"attributes": {
|
||||
"src": "cells_sim.v:60.11-60.12"
|
||||
}
|
||||
},
|
||||
"Y": {
|
||||
"hide_name": 0,
|
||||
"bits": [ 5 ],
|
||||
"attributes": {
|
||||
"src": "cells_sim.v:61.8-61.9"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"GAL_SOP": {
|
||||
"attributes": {
|
||||
"dynports": "00000000000000000000000000000001",
|
||||
"blackbox": "00000000000000000000000000000001",
|
||||
"cells_not_processed": "00000000000000000000000000000001",
|
||||
"src": "cells_sim.v:1.1-23.10"
|
||||
},
|
||||
"parameter_default_values": {
|
||||
"DEPTH": "00000000000000000000000000000000",
|
||||
"TABLE": "00000000000000000000000000000000",
|
||||
"WIDTH": "00000000000000000000000000000000"
|
||||
},
|
||||
"ports": {
|
||||
"A": {
|
||||
"direction": "input",
|
||||
"offset": -1,
|
||||
"upto": 1,
|
||||
"bits": [ 2, 3 ]
|
||||
},
|
||||
"Y": {
|
||||
"direction": "output",
|
||||
"bits": [ 4 ]
|
||||
}
|
||||
},
|
||||
"cells": {
|
||||
},
|
||||
"netnames": {
|
||||
"A": {
|
||||
"hide_name": 0,
|
||||
"bits": [ 2, 3 ],
|
||||
"offset": -1,
|
||||
"upto": 1,
|
||||
"attributes": {
|
||||
"src": "cells_sim.v:6.20-6.21"
|
||||
}
|
||||
},
|
||||
"Y": {
|
||||
"hide_name": 0,
|
||||
"bits": [ 4 ],
|
||||
"attributes": {
|
||||
"src": "cells_sim.v:7.13-7.14"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"olmc_test": {
|
||||
"attributes": {
|
||||
"top": "00000000000000000000000000000001",
|
||||
"src": "testcases/olmc_test.v:1.1-15.10"
|
||||
},
|
||||
"ports": {
|
||||
"clk": {
|
||||
"direction": "input",
|
||||
"bits": [ 2 ]
|
||||
},
|
||||
"A": {
|
||||
"direction": "input",
|
||||
"bits": [ 3 ]
|
||||
},
|
||||
"B": {
|
||||
"direction": "input",
|
||||
"bits": [ 4 ]
|
||||
},
|
||||
"AND": {
|
||||
"direction": "output",
|
||||
"bits": [ 5 ]
|
||||
},
|
||||
"NAND": {
|
||||
"direction": "output",
|
||||
"bits": [ 6 ]
|
||||
},
|
||||
"REG_AND": {
|
||||
"direction": "output",
|
||||
"bits": [ 7 ]
|
||||
},
|
||||
"REG_NAND": {
|
||||
"direction": "output",
|
||||
"bits": [ 8 ]
|
||||
}
|
||||
},
|
||||
"cells": {
|
||||
"$abc$98$auto$blifparse.cc:519:parse_blif$100": {
|
||||
"hide_name": 1,
|
||||
"type": "GAL_OLMC",
|
||||
"parameters": {
|
||||
"INVERTED": "1",
|
||||
"REGISTERED": "0"
|
||||
},
|
||||
"attributes": {
|
||||
"module_not_derived": "00000000000000000000000000000001",
|
||||
"src": "techmaps/pla.v:37.6-40.5|techmaps/trivial_sop.v:12.11-12.43|techmaps/olmc_comb.v:28.5-33.4"
|
||||
},
|
||||
"port_directions": {
|
||||
"A": "input",
|
||||
"C": "input",
|
||||
"E": "input",
|
||||
"Y": "inout"
|
||||
},
|
||||
"connections": {
|
||||
"A": [ 9 ],
|
||||
"C": [ "x" ],
|
||||
"E": [ "1" ],
|
||||
"Y": [ 6 ]
|
||||
}
|
||||
},
|
||||
"$abc$98$auto$blifparse.cc:519:parse_blif$99": {
|
||||
"hide_name": 1,
|
||||
"type": "GAL_SOP",
|
||||
"parameters": {
|
||||
"DEPTH": "00000000000000000000000000000001",
|
||||
"TABLE": "1010",
|
||||
"WIDTH": "00000000000000000000000000000010"
|
||||
},
|
||||
"attributes": {
|
||||
"module_not_derived": "00000000000000000000000000000001",
|
||||
"src": "techmaps/pla.v:37.6-40.5|techmaps/trivial_sop.v:20.6-23.5"
|
||||
},
|
||||
"port_directions": {
|
||||
"A": "input",
|
||||
"Y": "output"
|
||||
},
|
||||
"connections": {
|
||||
"A": [ 10, 11 ],
|
||||
"Y": [ 9 ]
|
||||
}
|
||||
},
|
||||
"$auto$ff.cc:266:slice$93": {
|
||||
"hide_name": 1,
|
||||
"type": "GAL_OLMC",
|
||||
"parameters": {
|
||||
"INVERTED": "0",
|
||||
"REGISTERED": "1"
|
||||
},
|
||||
"attributes": {
|
||||
"module_not_derived": "00000000000000000000000000000001",
|
||||
"src": "testcases/olmc_test.v:10.1-13.4|techmaps/olmc_seq.v:10.5-15.4"
|
||||
},
|
||||
"port_directions": {
|
||||
"A": "input",
|
||||
"C": "input",
|
||||
"E": "input",
|
||||
"Y": "inout"
|
||||
},
|
||||
"connections": {
|
||||
"A": [ 9 ],
|
||||
"C": [ 12 ],
|
||||
"E": [ "1" ],
|
||||
"Y": [ 7 ]
|
||||
}
|
||||
},
|
||||
"$auto$ff.cc:266:slice$94": {
|
||||
"hide_name": 1,
|
||||
"type": "GAL_OLMC",
|
||||
"parameters": {
|
||||
"INVERTED": "0",
|
||||
"REGISTERED": "1"
|
||||
},
|
||||
"attributes": {
|
||||
"module_not_derived": "00000000000000000000000000000001",
|
||||
"src": "testcases/olmc_test.v:10.1-13.4|techmaps/olmc_seq.v:10.5-15.4"
|
||||
},
|
||||
"port_directions": {
|
||||
"A": "input",
|
||||
"C": "input",
|
||||
"E": "input",
|
||||
"Y": "inout"
|
||||
},
|
||||
"connections": {
|
||||
"A": [ 6 ],
|
||||
"C": [ 12 ],
|
||||
"E": [ "1" ],
|
||||
"Y": [ 8 ]
|
||||
}
|
||||
},
|
||||
"$iopadmap$olmc_test.A": {
|
||||
"hide_name": 1,
|
||||
"type": "GAL_INPUT",
|
||||
"parameters": {
|
||||
},
|
||||
"attributes": {
|
||||
"keep": "00000000000000000000000000000001"
|
||||
},
|
||||
"port_directions": {
|
||||
"A": "input",
|
||||
"Y": "output"
|
||||
},
|
||||
"connections": {
|
||||
"A": [ 3 ],
|
||||
"Y": [ 11 ]
|
||||
}
|
||||
},
|
||||
"$iopadmap$olmc_test.AND": {
|
||||
"hide_name": 1,
|
||||
"type": "GAL_OLMC",
|
||||
"parameters": {
|
||||
"INVERTED": "0",
|
||||
"REGISTERED": "0"
|
||||
},
|
||||
"attributes": {
|
||||
"keep": "00000000000000000000000000000001",
|
||||
"module_not_derived": "00000000000000000000000000000001",
|
||||
"src": "techmaps/olmc_comb.v:10.5-15.4"
|
||||
},
|
||||
"port_directions": {
|
||||
"A": "input",
|
||||
"C": "input",
|
||||
"E": "input",
|
||||
"Y": "inout"
|
||||
},
|
||||
"connections": {
|
||||
"A": [ 9 ],
|
||||
"C": [ "x" ],
|
||||
"E": [ "1" ],
|
||||
"Y": [ 5 ]
|
||||
}
|
||||
},
|
||||
"$iopadmap$olmc_test.B": {
|
||||
"hide_name": 1,
|
||||
"type": "GAL_INPUT",
|
||||
"parameters": {
|
||||
},
|
||||
"attributes": {
|
||||
"keep": "00000000000000000000000000000001"
|
||||
},
|
||||
"port_directions": {
|
||||
"A": "input",
|
||||
"Y": "output"
|
||||
},
|
||||
"connections": {
|
||||
"A": [ 4 ],
|
||||
"Y": [ 10 ]
|
||||
}
|
||||
},
|
||||
"$iopadmap$olmc_test.clk": {
|
||||
"hide_name": 1,
|
||||
"type": "GAL_INPUT",
|
||||
"parameters": {
|
||||
},
|
||||
"attributes": {
|
||||
"keep": "00000000000000000000000000000001"
|
||||
},
|
||||
"port_directions": {
|
||||
"A": "input",
|
||||
"Y": "output"
|
||||
},
|
||||
"connections": {
|
||||
"A": [ 2 ],
|
||||
"Y": [ 12 ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"netnames": {
|
||||
"$abc$98$iopadmap$A": {
|
||||
"hide_name": 1,
|
||||
"bits": [ 11 ],
|
||||
"attributes": {
|
||||
}
|
||||
},
|
||||
"$abc$98$iopadmap$B": {
|
||||
"hide_name": 1,
|
||||
"bits": [ 10 ],
|
||||
"attributes": {
|
||||
}
|
||||
},
|
||||
"$iopadmap$AND": {
|
||||
"hide_name": 1,
|
||||
"bits": [ 9 ],
|
||||
"attributes": {
|
||||
}
|
||||
},
|
||||
"$iopadmap$clk": {
|
||||
"hide_name": 1,
|
||||
"bits": [ 12 ],
|
||||
"attributes": {
|
||||
}
|
||||
},
|
||||
"A": {
|
||||
"hide_name": 0,
|
||||
"bits": [ 3 ],
|
||||
"attributes": {
|
||||
"src": "testcases/olmc_test.v:3.12-3.13"
|
||||
}
|
||||
},
|
||||
"AND": {
|
||||
"hide_name": 0,
|
||||
"bits": [ 5 ],
|
||||
"attributes": {
|
||||
"src": "testcases/olmc_test.v:4.8-4.11"
|
||||
}
|
||||
},
|
||||
"B": {
|
||||
"hide_name": 0,
|
||||
"bits": [ 4 ],
|
||||
"attributes": {
|
||||
"src": "testcases/olmc_test.v:3.15-3.16"
|
||||
}
|
||||
},
|
||||
"NAND": {
|
||||
"hide_name": 0,
|
||||
"bits": [ 6 ],
|
||||
"attributes": {
|
||||
"src": "testcases/olmc_test.v:4.13-4.17"
|
||||
}
|
||||
},
|
||||
"REG_AND": {
|
||||
"hide_name": 0,
|
||||
"bits": [ 7 ],
|
||||
"attributes": {
|
||||
"src": "testcases/olmc_test.v:5.12-5.19"
|
||||
}
|
||||
},
|
||||
"REG_NAND": {
|
||||
"hide_name": 0,
|
||||
"bits": [ 8 ],
|
||||
"attributes": {
|
||||
"src": "testcases/olmc_test.v:5.21-5.29"
|
||||
}
|
||||
},
|
||||
"clk": {
|
||||
"hide_name": 0,
|
||||
"bits": [ 2 ],
|
||||
"attributes": {
|
||||
"src": "testcases/olmc_test.v:3.7-3.10"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
26
compiler/tests/yosys_parser_test.rs
Normal file
26
compiler/tests/yosys_parser_test.rs
Normal file
|
|
@ -0,0 +1,26 @@
|
|||
use ver2gal::yosys_parser::*;
|
||||
use std::error::Error;
|
||||
use std::fs;
|
||||
use serde_json::from_slice;
|
||||
|
||||
#[test]
|
||||
fn test_load() -> Result<(), Box<dyn Error>> {
|
||||
let f = fs::read("testcases/json/synth_olmc_test.json")?;
|
||||
|
||||
let data: YosysDoc = from_slice(f.as_slice())?;
|
||||
println!("{:?}", data);
|
||||
|
||||
Ok(())
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn test_graph() -> Result<(), Box<dyn Error>> {
|
||||
let f = fs::read("testcases/json/synth_olmc_test.json")?;
|
||||
|
||||
let data: YosysDoc = from_slice(f.as_slice())?;
|
||||
|
||||
let g = Graph::from(data);
|
||||
println!("{:?}", g);
|
||||
g.validate()?;
|
||||
Ok(())
|
||||
}
|
||||
Loading…
Reference in a new issue