saji/yosys4gal
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mirror of https://github.com/annoyatron255/yosys4gal.git synced 2024-12-22 10:42:24 +00:00
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Author SHA1 Message Date
saji b10e261681 mvp: and gate outputs something 2024-05-04 16:28:09 -05:00
saji 4154a18e90 partially working 2024-05-04 15:06:28 -05:00
saji a550d84750 bugfixes, working on SOP stuff 2024-05-04 15:06:28 -05:00
annoyatron255 5ac484b1a8
Add initial Verilog model for the GAL16V8 2024-05-03 21:44:22 -05:00
saji bb48e10488 wip: commit before refactor of graph code 2024-05-03 11:14:32 -05:00
saji 8bfcd28e0d port mapping, inputs on OLMC outputs consume the OLMC 2024-05-02 17:39:36 -05:00
saji 2ad9a1d157 wip: newtype nodeindex 2024-05-02 16:11:24 -05:00
saji 0be535bfcb wip: deferred OLMC mapping stuff 2024-05-02 15:49:05 -05:00
saji 62180c852f wip: fitter 2024-05-02 12:38:57 -05:00
saji 9d2befc29b added rust tool 2024-04-28 22:44:18 -05:00
annoyatron255 87efbe693d
Remove extra shell command 2024-04-06 00:33:41 -05:00
annoyatron255 56bee7db76
Add tristates 2024-04-04 20:39:30 -05:00
annoyatron255 2d6fe23577
Cleanup 2024-04-04 18:08:40 -05:00
annoyatron255 f565bf576d
Some edge cases cleaned up 2024-04-04 17:16:02 -05:00
annoyatron255 e9a9c68f88
Add OLMC on internal combinational nodes 2024-04-04 13:54:11 -05:00
annoyatron255 8c695d0fb3
Cleanup 2024-04-04 12:02:51 -05:00
annoyatron255 f20410a723
Add OLMCs 2024-04-04 01:33:47 -05:00
annoyatron255 bdf468eef5
make TCL 2024-03-18 02:12:59 -05:00
annoyatron255 fce164299a
initial commit 2024-03-18 00:06:49 -05:00