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Verilog Flow for the GAL16V8 and GAL22V10
1 commit 1 branch 0 tags 154 KiB
Rust 58.6%
Verilog 30.2%
Tcl 10.2%
Shell 1%
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annoyatron255 fce164299a
initial commit
2024-03-18 00:06:49 -05:00
gal_dff.lib initial commit 2024-03-18 00:06:49 -05:00
inv_techmap.v initial commit 2024-03-18 00:06:49 -05:00
macrocell.v initial commit 2024-03-18 00:06:49 -05:00
pla.v initial commit 2024-03-18 00:06:49 -05:00
pre_techmap.json initial commit 2024-03-18 00:06:49 -05:00
synth_gal.ys initial commit 2024-03-18 00:06:49 -05:00
test.v initial commit 2024-03-18 00:06:49 -05:00
test.v.old initial commit 2024-03-18 00:06:49 -05:00
test_synth.blif initial commit 2024-03-18 00:06:49 -05:00
test_synth.json initial commit 2024-03-18 00:06:49 -05:00
test_synth.rtlil initial commit 2024-03-18 00:06:49 -05:00
test_synth.txt initial commit 2024-03-18 00:06:49 -05:00
test_synth.v initial commit 2024-03-18 00:06:49 -05:00