saji/yosys4gal
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Verilog Flow for the GAL16V8 and GAL22V10
2 commits 1 branch 0 tags 154 KiB
Rust 58.6%
Verilog 30.2%
Tcl 10.2%
Shell 1%
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annoyatron255 bdf468eef5
make TCL
2024-03-18 02:12:59 -05:00
extractions make TCL 2024-03-18 02:12:59 -05:00
techmaps make TCL 2024-03-18 02:12:59 -05:00
synth_gal.tcl make TCL 2024-03-18 02:12:59 -05:00
test.v make TCL 2024-03-18 02:12:59 -05:00