Commit graph

65 commits

Author SHA1 Message Date
Saji 3d49afe6ed rename bitslicer to hub75, rework hub75ctrl sig 2024-09-27 16:27:52 -05:00
Saji c328d174ad skip platform tests when toolchain missing 2024-09-27 16:27:38 -05:00
Saji ef3df3ae92 format code 2024-09-27 01:06:47 -05:00
Saji bcac3d0dcd make basic config module 2024-09-27 01:06:11 -05:00
Saji 7e41e6e2f3 make flake use custom amaranth
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2024-09-26 10:34:07 -05:00
Saji 3205c7104e update ci test flow
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2024-09-26 10:03:57 -05:00
Saji ccdbc98cb0 add flake/nix formatter (nixfmt)
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2024-09-26 01:46:28 -05:00
Saji 79927f0cbd flake now works with pyproject and flake-parts 2024-09-25 19:21:38 -05:00
Saji 20054ad034 add amaranth-boards, wip main package
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2024-09-24 20:53:12 -05:00
saji b25ab8bd52 start working on making flake work
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2024-09-24 01:43:25 -05:00
saji 63811b929a add amaranth-boards to pdm, add platform pins 2024-09-24 01:42:08 -05:00
saji 3188fdefa5 wip: test works, bypass amaranth-boards not working 2024-09-22 01:32:44 -05:00
saji 20b16b6d40 add board,platform, wip cli
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2024-09-21 22:53:46 -05:00
Saji c601248cf2 move things into common
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2024-09-21 14:38:01 -05:00
Saji 5820d80db2 add bbox construction tests, gamma docstring
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2024-09-21 10:05:24 -05:00
saji dd47014029 fix geom, add unittest
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2024-09-20 23:29:50 -05:00
saji 477966b9c8 migrate tests 2024-09-20 23:29:42 -05:00
saji 75d6e15b42 add gamma module 2024-09-20 23:05:15 -05:00
saji 29464f91b4 add intersection 2024-09-20 19:05:18 -05:00
saji c6a81b5a76 initial coordinator 2024-09-20 15:51:59 -05:00
saji fbb39a85e5 added geometry module 2024-09-20 14:59:17 -05:00
saji 66b492e147 refactor around rgb666
remove 4xclocking for double-fetch architecture (still using 2xclock for
better S/H)
2024-09-19 01:45:01 -05:00
saji fe4a902bd8 adjustment
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2024-09-10 23:19:52 -05:00
saji ca472d7112 update tests
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2024-09-10 15:19:13 -05:00
saji 386403bd12 add swapbank + test
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2024-09-09 17:46:50 -05:00
saji 7a4de2e02d checkin
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2024-09-03 11:15:59 -05:00
saji d42e227c4d add wip sdram controller, start multistring hub75
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2024-08-23 20:06:29 -05:00
saji bf35262640 add pytest 2024-08-23 18:02:26 -05:00
saji 1ccc0b3d39 remove old groovylight code
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2024-08-21 16:22:16 -05:00
saji 83bb38ba6d initial effort 2024-08-21 16:20:40 -05:00
saji f3789b6432 sokol works, working on nix tooling
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2024-05-26 08:48:38 -05:00
saji 4b570ad5a5 Update sim/src/main.cpp
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2024-05-25 17:33:36 +00:00
saji 8354677908 fix ci
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2024-05-25 12:16:18 -05:00
saji 46a42180ed fix first pixel errors.
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Moved the tests to a separate program to make way for sokol.
2024-05-25 12:04:12 -05:00
saji 905f61c814 fix cycle latency, broke first pixel
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2024-05-24 01:23:49 -05:00
saji 70de66231b remove doc
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2024-05-24 00:42:37 -05:00
saji 1628edad62 add basic mdbook doc
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2024-05-23 12:07:53 -05:00
saji 37b813a015 cleanup, use checks instead of requires
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2024-05-23 11:58:44 -05:00
saji c7fde88baf Update README.md
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2024-05-23 06:21:48 +00:00
saji 7c7ccf81fc use ninja instead
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2024-05-23 00:43:33 -05:00
saji fdca36f9ce add nix caching
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2024-05-23 00:36:53 -05:00
saji 7cd0e1c53c fix bram behavior, adjust row offset
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2024-05-23 00:34:26 -05:00
saji 32deb30c92 add gitea actions 2024-05-23 00:33:20 -05:00
saji d465fccaed wip: refactor and fix rightmost pixel bug
hack but now row1 doesn't work.
2024-05-22 22:26:33 -05:00
saji 2a7908eae9 wip: line scan test
also factored out some code.
2024-05-22 15:59:38 -05:00
saji da9c0c05a7 wip: text fixture refactor 2024-05-21 18:08:29 -05:00
saji 3a76a55e56 added more gitignore 2024-05-19 18:17:30 -05:00
saji d4df01f5c6 add basic verilator sim 2024-05-19 00:15:53 -05:00
saji b248c4d731 increase speed grade of chip to meet timing for bram 2024-05-10 11:31:51 -05:00
saji bcb463a8d0 wip: 4x clock double-read bram 2024-05-09 17:31:15 -05:00