fix bram behavior, adjust row offset

sim/inc/tests.hpp

@@ -4,15 +4,14 @@
 #include "verilated.h"
 #include "verilated_vcd_c.h"
 #include <cstdint>
-#include <span>
 #include <memory>
 #include <queue>
+#include <span>
 #include <vector>
 
-
 // represents a generic co-simulated device.
-// While this abstract class is very simple, it enables dynamic behavior to be added to the
-// simulation fixture.
+// While this abstract class is very simple, it enables dynamic behavior to be
+// added to the simulation fixture.
 class CosimulatedDevice {
 public:
   virtual ~CosimulatedDevice(){};
@@ -20,7 +19,6 @@ public:
   virtual void tick() = 0;
 };
 
-
 // Simple stimulus class used to trigger basic operations
 class PulseStimulus : public CosimulatedDevice {
   unsigned long width;
@@ -51,6 +49,7 @@ class FakeBRAM : public CosimulatedDevice {
   unsigned long &data_out;
 
   unsigned char &clk;
+  unsigned char prev_clk;
 
 public:
   FakeBRAM(int latency, unsigned char &clk, unsigned short &addr_in,
@@ -68,16 +67,20 @@ public:
     for (int i = 0; i < latency; i++) {
       addr_lookup_q.push(0);
     }
+    prev_clk = clk;
   }
 
   void tick() {
     // we push and pop in the same tick: this way we keep the queue the same
     // size, acting as a pipeline delay.
-    addr_lookup_q.push(addr_in);
+    if (prev_clk == 0 && clk == 1) { // rising edge
+      addr_lookup_q.push(addr_in);
 
-    auto addr_to_load = addr_lookup_q.front();
-    addr_lookup_q.pop();
-    data_out = ram.at(addr_to_load);
+      auto addr_to_load = addr_lookup_q.front();
+      addr_lookup_q.pop();
+      data_out = ram.at(addr_to_load);
+    }
+    prev_clk = clk;
   }
 
   // TODO: allow accessing/setting the data
@@ -86,14 +89,10 @@ public:
   void write(unsigned short addr, unsigned long data) { ram[addr] = data; }
 };
 
-
 // test fixture to reduce amount of runtime code.
 // Supports:
 // adding external modules
 // running the test
-// storing if the done flag was raised (or not)
-//
-// TODO: tracing.
 template <typename DUT> class VerilatorTestFixture {
 public:
   enum class FinishReason { Ok, Timeout };

sim/src/main.cpp

@@ -58,7 +58,7 @@ TEST_CASE("HUB75E Driver Test") {
     // this is the part where we validate that the line in = line out.
     // we have to generate different values since the
     fixture.enable_trace("testing.vcd");
-    auto line = GENERATE(take(10, chunk(256, random(0, 0xFFFFFF))));
+    auto line = GENERATE(take(10, chunk(512, random(0, 0xFFFFFF))));
     auto bram = std::make_shared<FakeBRAM>(1, dut.clk, dut.pixbuf_addr,
                                            dut.pixbuf_data);
 
@@ -81,8 +81,8 @@ TEST_CASE("HUB75E Driver Test") {
       CAPTURE(i);
       CAPTURE(ram_ref[i], row0[i]);
       REQUIRE(ram_ref[i] == row0[i]);
-      CAPTURE(ram_ref[i+128], row1[i]);
-      REQUIRE(ram_ref[i+128] == row1[i]);
+      CAPTURE(ram_ref[i+256], row1[i]);
+      REQUIRE(ram_ref[i+256] == row1[i]);
 
     }
     // CHECK(std::equal(ram_ref.begin(), ram_ref.begin() + 128, row0.begin(),