fix cycle latency, broke first pixel

2024-05-24 01:23:49 -05:00 · 2024-05-24 01:23:49 -05:00 · 905f61c814
parent 70de66231b
commit 905f61c814
1 changed files with 3 additions and 3 deletions
--- a/verilog/hub75e.sv
+++ b/verilog/hub75e.sv
@ -116,12 +116,12 @@ module hub75e (
            end
            2'b00: begin  // falling edge
              // load pixel 2
-              panel_rgb1 <= ram_rgb_slice;
-              pixnum <= pixnum - 1;
-              pixrow <= 0;
            end
            2'b01: begin  // midpoint of low clk
+              panel_rgb1 <= ram_rgb_slice;
              // decrement pixnum
+              pixnum <= pixnum - 1;
+              pixrow <= 0;
            end
            default: begin
            end