diff --git a/verilog/hub75e.sv b/verilog/hub75e.sv
index ea578f3..b578011 100644
--- a/verilog/hub75e.sv
+++ b/verilog/hub75e.sv
@@ -116,12 +116,12 @@ module hub75e (
             end
             2'b00: begin  // falling edge
               // load pixel 2
-              panel_rgb1 <= ram_rgb_slice;
-              pixnum <= pixnum - 1;
-              pixrow <= 0;
             end
             2'b01: begin  // midpoint of low clk
+              panel_rgb1 <= ram_rgb_slice;
               // decrement pixnum
+              pixnum <= pixnum - 1;
+              pixrow <= 0;
             end
             default: begin
             end