From 905f61c814d10bd1d3fc3db3c4b0774d29dd03a0 Mon Sep 17 00:00:00 2001
From: saji <saji@saji.dev>
Date: Fri, 24 May 2024 01:23:49 -0500
Subject: [PATCH] fix cycle latency, broke first pixel

---
 verilog/hub75e.sv | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/verilog/hub75e.sv b/verilog/hub75e.sv
index ea578f3..b578011 100644
--- a/verilog/hub75e.sv
+++ b/verilog/hub75e.sv
@@ -116,12 +116,12 @@ module hub75e (
             end
             2'b00: begin  // falling edge
               // load pixel 2
-              panel_rgb1 <= ram_rgb_slice;
-              pixnum <= pixnum - 1;
-              pixrow <= 0;
             end
             2'b01: begin  // midpoint of low clk
+              panel_rgb1 <= ram_rgb_slice;
               // decrement pixnum
+              pixnum <= pixnum - 1;
+              pixrow <= 0;
             end
             default: begin
             end