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cleanup, use checks instead of requires
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Verilator Unit Tests / Test (push) Failing after 5m18s
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saji 2024-05-23 11:57:50 -05:00
parent c7fde88baf
commit 37b813a015
1 changed files with 12 additions and 16 deletions
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28
sim/src/main.cpp
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@ -15,17 +15,18 @@ TEST_CASE("HUB75E Driver Test") {
};
fixture.set_done_callback(done_check);
const Vhub75e &dut = fixture.get();
// stimulus to start the transaction.
auto stim = std::make_shared<PulseStimulus>(dut.write_trig, 4);
fixture.set_timeout(250000);
fixture.add_module(stim);
fixture.set_timeout(250000);
auto bram = std::make_shared<FakeBRAM>(1, dut.clk, dut.pixbuf_addr,
dut.pixbuf_data);
fixture.add_module(bram);
auto display = std::make_shared<HUB75Reciever>(128, 64, dut);
fixture.add_module(display);
SECTION("Smoke Tests") {
auto bram = std::make_shared<FakeBRAM>(1, dut.clk, dut.pixbuf_addr,
dut.pixbuf_data);
fixture.add_module(bram);
auto display = std::make_shared<HUB75Reciever>(128, 64, dut);
fixture.add_module(display);
fixture.exec();
@ -58,14 +59,9 @@ TEST_CASE("HUB75E Driver Test") {
// this is the part where we validate that the line in = line out.
// we have to generate different values since the
fixture.enable_trace("testing.vcd");
auto line = GENERATE(take(10, chunk(512, random(0, 0xFFFFFF))));
auto bram = std::make_shared<FakeBRAM>(1, dut.clk, dut.pixbuf_addr,
dut.pixbuf_data);
// generate an entire block of RAM
auto line = GENERATE(take(1, chunk(512, random(0, 0xFFFFFF))));
std::copy(line.begin(), line.end(), bram->get().begin());
fixture.add_module(bram);
auto display = std::make_shared<HUB75Reciever>(128, 64, dut);
fixture.add_module(display);
fixture.exec();
@ -80,9 +76,9 @@ TEST_CASE("HUB75E Driver Test") {
for (int i = 0; i < 128; i++) {
CAPTURE(i);
CAPTURE(ram_ref[i], row0[i]);
REQUIRE(ram_ref[i] == row0[i]);
CHECK(ram_ref[i] == row0[i]);
CAPTURE(ram_ref[i+256], row1[i]);
REQUIRE(ram_ref[i+256] == row1[i]);
CHECK(ram_ref[i+256] == row1[i]);
}
// CHECK(std::equal(ram_ref.begin(), ram_ref.begin() + 128, row0.begin(),