12 commits

Author	SHA1	Message	Date
saji	905f61c814	fix cycle latency, broke first pixel	2024-05-24 01:23:49 -05:00
saji	d465fccaed	wip: refactor and fix rightmost pixel bug ... hack but now row1 doesn't work.	2024-05-22 22:26:33 -05:00
saji	d4df01f5c6	add basic verilator sim	2024-05-19 00:15:53 -05:00
saji	b248c4d731	increase speed grade of chip to meet timing for bram	2024-05-10 11:31:51 -05:00
saji	bcb463a8d0	wip: 4x clock double-read bram	2024-05-09 17:31:15 -05:00
saji	2a8c70bab2	fix bit-loading latency using comb logic ... make frame counter for generating data	2024-05-02 20:30:51 -05:00
saji	37dabd603a	coordinator works now ... fixed some off by one errors to make the screen work good	2024-05-01 16:14:32 -05:00
saji	9a4dfea4f0	wip: basic pixel generator + coordinator module ... coordinator is a high level hub75 controller. It drives multiple panels by generating the x/y coordinates that would be displayed on each, then converting those into the BRAM format to be written quickly.	2024-04-30 23:48:10 -05:00
saji	bd2fa51f2d	wip: bitslicer	2024-04-30 01:41:31 -05:00
saji	31d612a2e8	wip: attempt at integrating, fail	2024-04-30 00:29:41 -05:00
saji	75ef4ad594	bram stuff	2024-04-29 01:16:36 -05:00
saji	00ebfa8009	initial verilog	2024-04-28 16:42:41 -05:00