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saji
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groovylight
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b248c4d731
groovylight
/
verilog
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saji
b248c4d731
increase speed grade of chip to meet timing for bram
2024-05-10 11:31:51 -05:00
..
tb
wip: 4x clock double-read bram
2024-05-09 17:31:15 -05:00
bitslicer.sv
coordinator works now
2024-05-01 16:14:32 -05:00
coordinator.sv
wip: 4x clock double-read bram
2024-05-09 17:31:15 -05:00
hub75e.sv
wip: 4x clock double-read bram
2024-05-09 17:31:15 -05:00
lineram.v
increase speed grade of chip to meet timing for bram
2024-05-10 11:31:51 -05:00
pixgen.sv
fix bit-loading latency using comb logic
2024-05-02 20:30:51 -05:00