groovylight/verilog
saji 905f61c814
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Verilator Unit Tests / Test (push) Failing after 5m13s
fix cycle latency, broke first pixel
2024-05-24 01:23:49 -05:00
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tb wip: 4x clock double-read bram 2024-05-09 17:31:15 -05:00
bitslicer.sv coordinator works now 2024-05-01 16:14:32 -05:00
coordinator.sv wip: 4x clock double-read bram 2024-05-09 17:31:15 -05:00
hub75e.sv fix cycle latency, broke first pixel 2024-05-24 01:23:49 -05:00
lineram.v add basic verilator sim 2024-05-19 00:15:53 -05:00
pixgen.sv fix bit-loading latency using comb logic 2024-05-02 20:30:51 -05:00