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16 lines
356 B
Verilog
16 lines
356 B
Verilog
module original (
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input wire clk,
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input wire [5:0] in,
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output reg [4:0] out
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);
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always @(posedge clk) begin
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out[0] <= in[0] && in[1];
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out[1] <= in[2] || in[3];
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out[2] <= in[4] && !in[5] || !in[4] && in[5];
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out[3] <= in[0] && in[1] && in[2] && in[3] && in[4] && in[5];
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out[4] <= !(in[0] || in[1] || in[2] || in[3] || in[4] || in[5]);
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end
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endmodule
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