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12 lines
236 B
Verilog
12 lines
236 B
Verilog
module complex_single_sop (clk, A, B, C,D, Y);
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input A, B, C, D;
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input clk;
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output reg Y;
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always @(posedge clk) begin
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Y <= (A && !B && !C && D) || (!A && B && !C && D) || (!A && !B && C && D) || (A && B && C && D);
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end
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endmodule
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