yosys4gal/testcases/complex_single_sop.v

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2024-05-04 23:16:30 +00:00
module complex_single_sop (clk, A, B, C,D, Y);
input A, B, C, D;
input clk;
output reg Y;
always @(posedge clk) begin
Y <= (A && !B && !C && D) || (!A && B && !C && D) || (!A && !B && C && D) || (A && B && C && D);
end
endmodule