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added and_gate_reg

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saji 2024-05-04 16:33:07 -05:00
parent 7b27f0f112
commit 2d6f0123cd
3 changed files with 17 additions and 0 deletions
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3
testcases/and_gate.pcf Normal file
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set_io A 2
set_io B 3
set_io Y 14

4
testcases/and_gate_reg.pcf Normal file
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set_io A 2
set_io B 3
set_io Y 14
set_io clk 1

10
testcases/and_gate_reg.v Normal file
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module and_gate (clk, A, B, Y);
input A, B;
output Y;
always @(posedge clk) begin
Y <= A && B;
end
endmodule