From 2d6f0123cd0d57e5449d1cfe881280860f1be124 Mon Sep 17 00:00:00 2001 From: saji Date: Sat, 4 May 2024 16:33:07 -0500 Subject: [PATCH] added and_gate_reg --- testcases/and_gate.pcf | 3 +++ testcases/and_gate_reg.pcf | 4 ++++ testcases/and_gate_reg.v | 10 ++++++++++ 3 files changed, 17 insertions(+) create mode 100644 testcases/and_gate.pcf create mode 100644 testcases/and_gate_reg.pcf create mode 100644 testcases/and_gate_reg.v diff --git a/testcases/and_gate.pcf b/testcases/and_gate.pcf new file mode 100644 index 0000000..842a155 --- /dev/null +++ b/testcases/and_gate.pcf @@ -0,0 +1,3 @@ +set_io A 2 +set_io B 3 +set_io Y 14 diff --git a/testcases/and_gate_reg.pcf b/testcases/and_gate_reg.pcf new file mode 100644 index 0000000..c635881 --- /dev/null +++ b/testcases/and_gate_reg.pcf @@ -0,0 +1,4 @@ +set_io A 2 +set_io B 3 +set_io Y 14 +set_io clk 1 diff --git a/testcases/and_gate_reg.v b/testcases/and_gate_reg.v new file mode 100644 index 0000000..4aef88a --- /dev/null +++ b/testcases/and_gate_reg.v @@ -0,0 +1,10 @@ +module and_gate (clk, A, B, Y); + +input A, B; +output Y; + +always @(posedge clk) begin + Y <= A && B; +end + +endmodule