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fix cycle latency, broke first pixel
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Verilator Unit Tests / Test (push) Failing after 5m13s
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saji 2024-05-24 01:23:49 -05:00
parent 70de66231b
commit 905f61c814
1 changed files with 3 additions and 3 deletions
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verilog/hub75e.sv
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@ -116,12 +116,12 @@ module hub75e (
end end
2'b00: begin // falling edge 2'b00: begin // falling edge
// load pixel 2 // load pixel 2
panel_rgb1 <= ram_rgb_slice;
pixnum <= pixnum - 1;
pixrow <= 0;
end end
2'b01: begin // midpoint of low clk 2'b01: begin // midpoint of low clk
panel_rgb1 <= ram_rgb_slice;
// decrement pixnum // decrement pixnum
pixnum <= pixnum - 1;
pixrow <= 0;
end end
default: begin default: begin
end end