mirror of
https://github.com/annoyatron255/yosys4gal.git
synced 2024-12-22 10:42:24 +00:00
11 lines
137 B
Verilog
11 lines
137 B
Verilog
module inout_tristate (
|
|
input a, b, c,
|
|
inout y,
|
|
output z
|
|
);
|
|
|
|
assign y = c && b ? a && b : 1'bz;
|
|
assign z = c ? a || b : y;
|
|
|
|
endmodule
|