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17 lines
338 B
Verilog
17 lines
338 B
Verilog
`default_nettype none
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module __wrapper (
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input wire __clk, // Pin 1
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input wire [7:0] __in, // Pin {9, 8, 7, 6, 5, 4, 3, 2}
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input wire __oe_n, // Pin 11
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inout wire [7:0] __io // Pin {12, 13, 14, 15, 16, 17, 18, 19}
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);
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GAL16V8_reg GAL16V8_reg_inst (
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.clk(__clk),
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.in(__in),
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.oe_n(__oe_n),
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.io(__io)
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);
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endmodule
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