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13 lines
274 B
Verilog
13 lines
274 B
Verilog
`default_nettype none
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module __wrapper (
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input wire [12:0] __in, // Pin {13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1}, 1 is clk
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inout wire [9:0] __io // Pin {14, 15, 16, 17, 18, 19, 20, 21, 22, 23}
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);
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GAL22V10_reg GAL22V10_reg_inst (
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.in(__in),
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.io(__io)
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);
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endmodule
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