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16 lines
262 B
Verilog
16 lines
262 B
Verilog
module olmc_test (clk, A, B, AND, NAND, REG_AND, REG_NAND);
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input clk, A, B;
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output AND, NAND;
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output reg REG_AND, REG_NAND;
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assign AND = A && B;
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assign NAND = !(A && B);
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always @ (posedge clk) begin
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REG_AND <= A && B;
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REG_NAND <= !(A && B);
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end
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endmodule
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