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41 lines
472 B
Verilog
41 lines
472 B
Verilog
module GAL_SOP (A, Y);
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parameter WIDTH = 0;
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parameter DEPTH = 0;
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parameter TABLE = 0;
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input [WIDTH-1:0] A;
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output reg Y;
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\$sop #(
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.WIDTH(WIDTH),
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.DEPTH(DEPTH),
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.TABLE(TABLE)
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) sop_partial (
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.A(A),
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.Y(Y)
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);
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endmodule
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module DFF_P (C, D, Q);
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input C, D;
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output Q;
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\$_DFF_P_ dff_inst (.C(C), .D(D), .Q(Q));
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endmodule
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module NDFF_P (C, D, Q);
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input C, D;
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output Q;
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wire Y;
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\$_NOT_ not_inst (.A(D), .Y(Y));
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\$_DFF_P_ dff_inst (.C(C), .D(Y), .Q(Q));
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endmodule
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