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31 lines
470 B
Verilog
31 lines
470 B
Verilog
module GAL22V10_reg_tb(
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output reg [12:0] in = 13'bx_xxxx_xxxx_xxx1,
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inout wire [9:0] io
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);
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GAL22V10_reg GAL22V10_reg_inst (
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.in(in),
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.io(io)
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);
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always #5 in[0] = !in[0];
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initial begin
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$dumpfile("dump.vcd");
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$dumpvars(0, GAL22V10_reg_tb);
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#3;
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in[12:1] = 12'bxxxx_xxxx_x00x;
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#10;
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in[12:1] = 12'bxxxx_xxxx_x01x;
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#10;
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in[12:1] = 12'bxxxx_xxxx_x10x;
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#10;
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in[12:1] = 12'bxxxx_xxxx_x11x;
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#10;
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in[12:1] = 12'bxxxx_xxxx_x00x;
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#10;
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$finish;
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end
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endmodule
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