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https://github.com/annoyatron255/yosys4gal.git
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84 lines
2.3 KiB
Verilog
84 lines
2.3 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company: Nobody
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// Engineer: Saji Champlin
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//
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// Create Date: 02/06/2020 11:53:40 AM
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// Design Name: MC14500B ICU
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// Module Name: mc14500b
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// Project Name: MC145k Computing system
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// Target Devices:
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// Tool Versions:
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// Description:
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// A dumb 1 bit computer with associated modules to allow for simple programs.
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// Dependencies:
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// None
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module mc14500b(
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input clk,
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input [3:0] i_inst,
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input i_data,
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output reg write,
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output reg jmp,
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output reg rtn,
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output reg flag0,
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output reg flagf,
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output reg o_rr,
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output reg o_data
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);
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reg ien, oen;
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reg skip;
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always @(posedge clk) begin
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// Reset any flags from last clock.
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jmp <= 0;
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rtn <= 0;
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flag0 <= 0;
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flagf <= 0;
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write <= 0; // FIX this it's not right technically.
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if (~skip) begin // skip
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case(i_inst)
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4'b0000 : flag0 <= 1; // NOPO
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4'b0001 : o_rr <= ien & i_data; // LD
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4'b0010 : o_rr <= ien & ~i_data; // LDC
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4'b0011 : o_rr <= ien & (i_data & o_rr); // AND
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4'b0100 : o_rr <= ien & (~i_data & o_rr); // NAND
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4'b0101 : o_rr <= ien & (i_data | o_rr); // OR
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4'b0110 : o_rr <= ien & (~i_data | o_rr); // NOR
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4'b0111 : o_rr <= ien & (o_rr == i_data); // XNOR
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4'b1000 : begin // STO
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// DATA -> RR, WRITE -> 1 for a clock (if oen is allowed).
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o_data <= oen & o_rr;
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write <= oen;
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end
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4'b1001 : begin // STOC
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// DATA -> ~RR, WRITE -> 1 for a clock.
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o_data <= ~o_rr;
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write <= oen;
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end
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4'b1010 : ien <= i_data;
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4'b1011 : oen <= i_data;
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4'b1100 : jmp <= 1;
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4'b1101 : begin // RTN
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rtn <= 1;
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skip <= 1;
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end
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4'b1110 : skip <= ~o_rr;
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4'b1111 : flagf <= 1;
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endcase
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end
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else begin // reset skip flag after clocking with skip once.
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skip <= 0;
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end
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end // neg edge
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// always @(posedge clk) begin
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// write <= 0;
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// end
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endmodule
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