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https://github.com/annoyatron255/yosys4gal.git
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54 lines
2.1 KiB
Markdown
54 lines
2.1 KiB
Markdown
_yosys4gal_: Verilog Flow for the GAL16V8 and GAL22V10
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======================================================
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A Verilog flow for GAL16V8 and GAL22V10 logic chips
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(and pin-compatible alternatives like the ATF16V8 and ATF22V10).
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It leverages [Yosys](https://www.github.com/YosysHQ/yosys)
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and [Galette](https://www.github.com/simon-frankau/galette).
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Usage
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-----
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To synthesize a Verilog file:
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```
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./synth_gal.tcl -- <VERILOG_FILE> [CHIP]
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```
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Where `[CHIP]` is either `GAL16V8` (default) or `GAL22V10`. The synthesized
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JSON netlist will be put in `output/`.
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To fit the synthesized design and generate the JEDEC file used for programming,
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first build the Rust compiler `ver2gal` (see the `compiler/` directory) and run:
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```
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./ver2gal synth <JSON NETLIST> <PCF_CONSTRAINTS> --chip <CHIP>
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```
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Where `<CHIP>` is either `gal16v8` or `gal22v10`. The generate JEDEC file will
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be generated in the current directory as `output.jed`. Note this program _must_
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be run in the same directory as the `shrink_sop.tcl` script.
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This JEDEC file can be optionally be verified programmatically using the
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scripts and Verilog models found the `models/` directory.
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The JEDEC file can then be flashed to the GAL chips. A convenience flashing
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script is provided for the cheap/common TL866 family of programmers. This works
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around the verification bugs in the upstream `minipro` programming software:
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```
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./flash_minipro.sh <JEDEC FILE> <CHIP>
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```
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Where `<CHIP>` is `GAL16V8`, `GAL22V10`, `ATF16V8B`, etc.
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Limitations
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-----------
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The GAL16V8 mode only supports the "Registered" mode and does not handle
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tristate Verilog for registered outputs (since they're globally shared). The
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GAL22V10 mode does not support the asynchronous set/reset signals for the
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registers. Additionally, in both modes, there is no guarantee that the mapping
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will be the most efficient (especially for timing). While fairly well tested,
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there is no guarantee of correctness either. Use at your own risk.
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Dependencies
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------------
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- `yosys` 0.38 or higher
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- Rust
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- `jedutil` from MAME utilities for model-based verification checking
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- `xxd` from Vim for model-based verification checking
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- `minipro` for the provided convenience flashing script
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