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https://github.com/annoyatron255/yosys4gal.git
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Some edge cases cleaned up
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commit
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@ -1,6 +1,17 @@
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#!/usr/bin/env -S yosys -c
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#!/usr/bin/env -S yosys -c
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yosys -import
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yosys -import
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set target "GAL16V8"
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if {$target == "GAL16V8"} {
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set num_max_products 7
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} elseif {$target == "GAL22V10"} {
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set num_max_products 11
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} else {
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puts "Invalid target chip"
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exit
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}
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if { $argc != 1 } {
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if { $argc != 1 } {
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puts "USAGE: $argv0 -- <VERILOG FILE>"
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puts "USAGE: $argv0 -- <VERILOG FILE>"
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exit
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exit
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@ -48,7 +59,9 @@ if {$num_regs > 0} { set num_inputs_regs [expr $num_inputs_regs - 1] }
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#yosys proc
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#yosys proc
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#techmap
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#techmap
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#select *
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#select *
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abc -sop -I $num_inputs_regs -P 7
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#abc -sop -I 100 -P $num_max_products
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abc -sop -I $num_inputs_regs -P $num_max_products
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opt
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opt
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clean -purge
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clean -purge
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@ -57,19 +70,21 @@ clean -purge
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## Tech mapping
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## Tech mapping
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# PLAs
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# PLAs
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techmap -map techmaps/pla.v -D PLA_MAX_PRODUCTS=7
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techmap -map techmaps/pla.v -D PLA_MAX_PRODUCTS=$num_max_products
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techmap -max_iter 1 -map techmaps/trivial_sop.v
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# Sequential OLMC
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# Sequential OLMC
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extract -constports -map extractions/ndff.v
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extract -constports -map extractions/ndff.v
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extract -constports -map extractions/olmc.v
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extract -constports -map extractions/olmc.v
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techmap -map techmaps/olmc_seq.v
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techmap -map techmaps/olmc_seq.v
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# Add OLMC for internal GAL_SOPs
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#techmap -max_iter 1 -map techmaps/pla_olmc_int.v */t:GAL_OLMC %ci2 */t:GAL_SOP %i */t:GAL_SOP %D
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techmap -max_iter 1 -map techmaps/pla_olmc_int.v */t:GAL_SOP %co1 */w:* %i */t:GAL_SOP %ci1 */w:* %i %i %c %ci1 %D
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# Combinational OLMC
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# Combinational OLMC
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iopadmap -bits -outpad GAL_COMB_OUTPUT_P A:Y */t:GAL_SOP "%x:+\[Y\]" */t:GAL_SOP %d o:* %i
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iopadmap -bits -outpad GAL_COMB_OUTPUT_P A:Y */t:GAL_SOP "%x:+\[Y\]" */t:GAL_SOP %d o:* %i
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techmap -map techmaps/olmc_comb.v o:* %x o:* %d
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techmap -map techmaps/olmc_comb.v
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# Add OLMC for internal GAL_SOPs
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techmap -max_iter 1 -map techmaps/pla_olmc_int.v */t:GAL_OLMC %ci2 */t:GAL_SOP %i */t:GAL_SOP %D
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clean -purge
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clean -purge
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26
techmaps/trivial_sop.v
Normal file
26
techmaps/trivial_sop.v
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@ -0,0 +1,26 @@
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(* techmap_celltype = "GAL_SOP" *)
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module _80_GAL_SOP (A, Y);
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parameter WIDTH = 0;
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parameter DEPTH = 0;
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parameter TABLE = 0;
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input [WIDTH-1:0] A;
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output reg Y;
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generate
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if (WIDTH == 1 && DEPTH == 1 && TABLE == 01) begin
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$_NOT_ _TECHMAP_REPLACE_ (.A(A), .Y(Y));
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end else if (WIDTH == 1 && DEPTH == 1 && TABLE == 10) begin
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$_BUF_ _TECHMAP_REPLACE_ (.A(A), .Y(Y));
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end else begin // No-op
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GAL_SOP #(
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.WIDTH(WIDTH),
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.DEPTH(DEPTH),
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.TABLE(TABLE)
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) _TECHMAP_REPLACE_ (
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.A(A),
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.Y(Y)
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);
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end
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endgenerate
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endmodule
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