wip: fitter debug for self-feedback

compiler/src/fitter.rs

@@ -38,6 +38,8 @@ fn get_sop_for_olmc(
     olmc_idx: &NodeIdx,
 ) -> Result<GalSop, MappingError> {
     let input = graph.get_node_port_conns(olmc_idx, "A");
+    debug!("Found connections into OLMC Input: {:?}", input);
+    debug!("OLMC {:?}", graph.get_node(olmc_idx));
     let sops_on_net: Vec<_> = input
         .iter()
         .filter_map(|i| {
@@ -46,9 +48,11 @@ fn get_sop_for_olmc(
                 return None;
             };
             let node = graph.get_node(&driver_cell.0)?;
+            debug!("Found driver node {:?}", node);
             match node {
                 Node::Sop(s) => Some(s.clone()),
                 Node::Olmc(o) => {
+                    debug!("Driver is another OLMC, creating dummy SOP, {:?}", o);
                     // find the row that contains this olmc.
                     // we know this exists because mapping has already finished.
                     let newsop = GalSop {

compiler/src/yosys_parser.rs

@@ -363,9 +363,9 @@ impl Graph {
                     .iter()
                     .enumerate()
                     .filter(|&(idx2, node2)| {
-                        if idx1 == idx2 {
-                            return false;
-                        }
+                        // if idx1 == idx2 {
+                        //     return false;
+                        // }
                         node2.get_nets().contains(&net)
                     })
                     .collect();

testcases/complex_single_sop.v

@@ -0,0 +1,11 @@
+module complex_single_sop (clk, A, B, C,D, Y);
+
+input A, B, C, D;
+input clk;
+output reg Y;
+
+always @(posedge clk) begin
+    Y <= (A && !B && !C && D) || (!A && B && !C && D) || (!A && !B && C && D) || (A && B && C && D);
+end
+
+endmodule

testcases/up_counter.pcf

@@ -0,0 +1,9 @@
+set_io clk 1
+set_io counter[0] 12
+set_io counter[1] 13
+set_io counter[2] 14
+set_io counter[3] 15
+set_io counter[4] 16
+set_io counter[5] 17
+set_io counter[6] 18
+set_io counter[7] 19

testcases/up_counter_downto.v

@@ -1,7 +1,7 @@
 module test (
 	input clk,
 
-	output reg [7:0] counter
+	output reg [6:0] counter
 );
 
 always @ (posedge clk) begin