saji/yosys4gal
1
0
Fork 0
mirror of https://github.com/annoyatron255/yosys4gal.git synced 2024-12-22 18:52:23 +00:00
Code Issues Packages Projects Releases Wiki Activity

wip: fitter debug for self-feedback

Browse source
This commit is contained in:
saji 2024-05-04 18:16:30 -05:00
parent 2e840d7cf4
commit 7ce252b0cb
5 changed files with 28 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
compiler/src/fitter.rs
View file

@ -38,6 +38,8 @@ fn get_sop_for_olmc(
olmc_idx: &NodeIdx, olmc_idx: &NodeIdx,
) -> Result<GalSop, MappingError> { ) -> Result<GalSop, MappingError> {
let input = graph.get_node_port_conns(olmc_idx, "A"); let input = graph.get_node_port_conns(olmc_idx, "A");
debug!("Found connections into OLMC Input: {:?}", input);
debug!("OLMC {:?}", graph.get_node(olmc_idx));
let sops_on_net: Vec<_> = input let sops_on_net: Vec<_> = input
.iter() .iter()
.filter_map(|i| { .filter_map(|i| {
@ -46,9 +48,11 @@ fn get_sop_for_olmc(
return None; return None;
}; };
let node = graph.get_node(&driver_cell.0)?; let node = graph.get_node(&driver_cell.0)?;
debug!("Found driver node {:?}", node);
match node { match node {
Node::Sop(s) => Some(s.clone()), Node::Sop(s) => Some(s.clone()),
Node::Olmc(o) => { Node::Olmc(o) => {
debug!("Driver is another OLMC, creating dummy SOP, {:?}", o);
// find the row that contains this olmc. // find the row that contains this olmc.
// we know this exists because mapping has already finished. // we know this exists because mapping has already finished.
let newsop = GalSop { let newsop = GalSop {

6
compiler/src/yosys_parser.rs
View file

@ -363,9 +363,9 @@ impl Graph {
.iter() .iter()
.enumerate() .enumerate()
.filter(|&(idx2, node2)| { .filter(|&(idx2, node2)| {
if idx1 == idx2 { // if idx1 == idx2 {
return false; // return false;
} // }
node2.get_nets().contains(&net) node2.get_nets().contains(&net)
}) })
.collect(); .collect();

11
testcases/complex_single_sop.v Normal file
View file

@ -0,0 +1,11 @@
module complex_single_sop (clk, A, B, C,D, Y);
input A, B, C, D;
input clk;
output reg Y;
always @(posedge clk) begin
Y <= (A && !B && !C && D) || (!A && B && !C && D) || (!A && !B && C && D) || (A && B && C && D);
end
endmodule

9
testcases/up_counter.pcf Normal file
View file

@ -0,0 +1,9 @@
set_io clk 1
set_io counter[0] 12
set_io counter[1] 13
set_io counter[2] 14
set_io counter[3] 15
set_io counter[4] 16
set_io counter[5] 17
set_io counter[6] 18
set_io counter[7] 19

2
testcases/up_counter_downto.v
View file

@ -1,7 +1,7 @@
module test ( module test (
input clk, input clk,
output reg [7:0] counter output reg [6:0] counter
); );
always @ (posedge clk) begin always @ (posedge clk) begin