2024-05-06 06:32:33 +00:00
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Techmaps
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========
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All the yosys techmapping libraries/Verilog files used for mapping to the GAL
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structure. See the `synth_gal.tcl` file for details on how they're used.
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A summary is below (in the order they're used):
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2024-05-06 06:42:29 +00:00
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- `gal_dff.lib` Liberty library for supported FFs (only positive edge-triggered
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DFFs). Used to prevent yosys from using fancy flip-flops
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2024-05-06 06:32:33 +00:00
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- `pla.v` splits SOPs into a chain of SOPs with a specified size
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- `trivial_sop.v` replaces SOPs which are just buffers/NOT gates with
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buffer/NOT cells
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2024-05-06 06:42:29 +00:00
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- `olmc_seq.v` converts all existing sequential elements into GAL_OLMCs this
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includes special merged types from other techmap passes/extractions
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2024-05-06 06:32:33 +00:00
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- `one_sop.v` converts GAL_SOPs with only one product into GAL_1SOPs. Used on
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enabled (tristate) lines
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- `pla_olmc_int.v` adds a combinational GAL_OLMC after a GAL_SOP. Used to
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insert GAL_OLMC between GAL_SOPs or enable lines
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- `olmc_comb.v` creates GAL_OLMCs for combinational/tristate output pads
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- `trivial_sop_olmc.v` adds a buffer GAL_SOP before a GAL_OLMC. Used to add
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GAL_SOPs between directly connect GAL_OLMCs/GAL_INPUTs
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- `trivial_1sop_olmc.v` same as above but for enable lines
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