generated from saji/ecp5-template
134 lines
2.9 KiB
Verilog
134 lines
2.9 KiB
Verilog
module lineram (
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input [35:0] din,
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input [8:0] addr_w,
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output reg [35:0] dout,
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input [8:0] addr_r,
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input write_en,
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input read_clk,
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input write_clk
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);
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`ifdef YOSYS
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// use the ECP5 primitive.
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PDPW16KD #(.REGMODE("OUTREG")) ram (
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.DI0 (din[0]),
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.DI1 (din[1]),
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.DI2 (din[2]),
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.DI3 (din[3]),
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.DI4 (din[4]),
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.DI5 (din[5]),
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.DI6 (din[6]),
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.DI7 (din[7]),
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.DI8 (din[8]),
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.DI9 (din[9]),
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.DI10(din[10]),
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.DI11(din[11]),
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.DI12(din[12]),
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.DI13(din[13]),
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.DI14(din[14]),
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.DI15(din[15]),
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.DI16(din[16]),
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.DI17(din[17]),
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.DI18(din[18]),
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.DI19(din[19]),
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.DI20(din[20]),
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.DI21(din[21]),
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.DI22(din[22]),
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.DI23(din[23]),
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.DI24(din[24]),
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.DI25(din[25]),
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.DI26(din[26]),
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.DI27(din[27]),
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.DI28(din[28]),
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.DI29(din[29]),
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.DI30(din[30]),
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.DI31(din[31]),
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.DI32(din[32]),
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.DI33(din[33]),
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.DI34(din[34]),
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.DI35(din[35]),
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.ADW0(addr_w[0]),
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.ADW1(addr_w[1]),
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.ADW2(addr_w[2]),
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.ADW3(addr_w[3]),
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.ADW4(addr_w[4]),
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.ADW5(addr_w[5]),
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.ADW6(addr_w[6]),
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.ADW7(addr_w[7]),
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.ADW8(addr_w[8]),
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.DO0 (dout[0]),
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.DO1 (dout[1]),
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.DO2 (dout[2]),
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.DO3 (dout[3]),
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.DO4 (dout[4]),
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.DO5 (dout[5]),
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.DO6 (dout[6]),
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.DO7 (dout[7]),
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.DO8 (dout[8]),
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.DO9 (dout[9]),
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.DO10(dout[10]),
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.DO11(dout[11]),
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.DO12(dout[12]),
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.DO13(dout[13]),
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.DO14(dout[14]),
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.DO15(dout[15]),
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.DO16(dout[16]),
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.DO17(dout[17]),
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.DO18(dout[18]),
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.DO19(dout[19]),
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.DO20(dout[20]),
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.DO21(dout[21]),
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.DO22(dout[22]),
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.DO23(dout[23]),
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.DO24(dout[24]),
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.DO25(dout[25]),
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.DO26(dout[26]),
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.DO27(dout[27]),
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.DO28(dout[28]),
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.DO29(dout[29]),
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.DO30(dout[30]),
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.DO31(dout[31]),
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.DO32(dout[32]),
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.DO33(dout[33]),
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.DO34(dout[34]),
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.DO35(dout[35]),
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.ADR0(addr_r[0]),
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.ADR1(addr_r[1]),
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.ADR2(addr_r[2]),
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.ADR3(addr_r[3]),
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.ADR4(addr_r[4]),
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.ADR5(addr_r[5]),
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.ADR6(addr_r[6]),
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.ADR7(addr_r[7]),
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.ADR8(addr_r[8]),
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.CER(1),
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.CEW(1),
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.CLKR(read_clk),
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.CLKW(write_clk),
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.CSW1(0),
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.CSW2(0),
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.CSW3(0),
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.CSR1(0),
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.CSR2(0),
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.CSR3(0),
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);
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`else
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reg [35:0] ram [2**9]/*verilator public*/;
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`ifndef YOSYS
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initial begin
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for (integer i = 0; i < 2 ** 9; i = i + 1) begin
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ram[i] = 0;
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end
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end
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`endif
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always @(posedge write_clk) begin
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if (write_en) ram[addr_w] <= din;
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end
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always @(posedge read_clk) begin
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dout <= ram[addr_r];
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end
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`endif
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endmodule
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