groovylight/verilog/lineram.v

module lineram (
    input [35:0] din,
    input [8:0] addr_w,
    output reg [35:0] dout,
    input [8:0] addr_r,
    input write_en,
    input read_clk,
    input write_clk
);

  `ifdef YOSYS
    // use the ECP5 primitive.
    PDPW16KD #(.REGMODE("OUTREG")) ram (
        .DI0 (din[0]),
        .DI1 (din[1]),
        .DI2 (din[2]),
        .DI3 (din[3]),
        .DI4 (din[4]),
        .DI5 (din[5]),
        .DI6 (din[6]),
        .DI7 (din[7]),
        .DI8 (din[8]),
        .DI9 (din[9]),
        .DI10(din[10]),
        .DI11(din[11]),
        .DI12(din[12]),
        .DI13(din[13]),
        .DI14(din[14]),
        .DI15(din[15]),
        .DI16(din[16]),
        .DI17(din[17]),
        .DI18(din[18]),
        .DI19(din[19]),
        .DI20(din[20]),
        .DI21(din[21]),
        .DI22(din[22]),
        .DI23(din[23]),
        .DI24(din[24]),
        .DI25(din[25]),
        .DI26(din[26]),
        .DI27(din[27]),
        .DI28(din[28]),
        .DI29(din[29]),
        .DI30(din[30]),
        .DI31(din[31]),
        .DI32(din[32]),
        .DI33(din[33]),
        .DI34(din[34]),
        .DI35(din[35]),
        .ADW0(addr_w[0]),
        .ADW1(addr_w[1]),
        .ADW2(addr_w[2]),
        .ADW3(addr_w[3]),
        .ADW4(addr_w[4]),
        .ADW5(addr_w[5]),
        .ADW6(addr_w[6]),
        .ADW7(addr_w[7]),
        .ADW8(addr_w[8]),
        .DO0 (dout[0]),
        .DO1 (dout[1]),
        .DO2 (dout[2]),
        .DO3 (dout[3]),
        .DO4 (dout[4]),
        .DO5 (dout[5]),
        .DO6 (dout[6]),
        .DO7 (dout[7]),
        .DO8 (dout[8]),
        .DO9 (dout[9]),
        .DO10(dout[10]),
        .DO11(dout[11]),
        .DO12(dout[12]),
        .DO13(dout[13]),
        .DO14(dout[14]),
        .DO15(dout[15]),
        .DO16(dout[16]),
        .DO17(dout[17]),
        .DO18(dout[18]),
        .DO19(dout[19]),
        .DO20(dout[20]),
        .DO21(dout[21]),
        .DO22(dout[22]),
        .DO23(dout[23]),
        .DO24(dout[24]),
        .DO25(dout[25]),
        .DO26(dout[26]),
        .DO27(dout[27]),
        .DO28(dout[28]),
        .DO29(dout[29]),
        .DO30(dout[30]),
        .DO31(dout[31]),
        .DO32(dout[32]),
        .DO33(dout[33]),
        .DO34(dout[34]),
        .DO35(dout[35]),
        .ADR0(addr_r[0]),
        .ADR1(addr_r[1]),
        .ADR2(addr_r[2]),
        .ADR3(addr_r[3]),
        .ADR4(addr_r[4]),
        .ADR5(addr_r[5]),
        .ADR6(addr_r[6]),
        .ADR7(addr_r[7]),
        .ADR8(addr_r[8]),
        .CER(1),
        .CEW(1),
        .CLKR(read_clk),
        .CLKW(write_clk),
        .CSW1(0),
        .CSW2(0),
        .CSW3(0),
        .CSR1(0),
        .CSR2(0),
        .CSR3(0),
    );
`else
  reg [35:0] ram [2**9]/*verilator public*/;

`ifndef YOSYS
  initial begin
    for (integer i = 0; i < 2 ** 9; i = i + 1) begin
      ram[i] = 0;
    end
  end
`endif

  always @(posedge write_clk) begin
    if (write_en) ram[addr_w] <= din;
  end
  always @(posedge read_clk) begin
    dout <= ram[addr_r];
  end
`endif
endmodule