generated from saji/ecp5-template
29 lines
592 B
Verilog
29 lines
592 B
Verilog
module lineram #(
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parameter DATA_WIDTH = 36,
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parameter ADDR_WIDTH = 9
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) (
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input [DATA_WIDTH - 1:0] din,
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input [ADDR_WIDTH - 1:0] addr_w,
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output reg [DATA_WIDTH - 1:0] dout,
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input [ADDR_WIDTH - 1:0] addr_r,
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input write_en,
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input read_clk,
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input write_clk
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);
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reg [DATA_WIDTH - 1] ram[2**ADDR_WIDTH];
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initial begin
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for(int i=0; i < 2**ADDR_WIDTH; i=i+1) begin
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ram[i] = 0;
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end
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end
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always @(posedge write_clk) begin
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if (write_en) ram[addr_w] <= din;
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end
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always @(posedge read_clk) begin
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dout <= ram[addr_r];
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end
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endmodule
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