module lineram #(
    parameter DATA_WIDTH = 36,
    parameter ADDR_WIDTH = 9
) (
    input [DATA_WIDTH - 1:0] din,
    input [ADDR_WIDTH - 1:0] addr_w,
    output reg [DATA_WIDTH - 1:0] dout,
    input [ADDR_WIDTH - 1:0] addr_r,
    input write_en,
    input read_clk,
    input write_clk
);

  reg [DATA_WIDTH - 1] ram[2**ADDR_WIDTH];

  initial begin
    for(int i=0; i < 2**ADDR_WIDTH; i=i+1) begin
      ram[i] = 0;
    end
  end

  always @(posedge write_clk) begin
    if (write_en) ram[addr_w] <= din;
  end
  always @(posedge read_clk) begin
    dout <= ram[addr_r];
  end
endmodule