generated from saji/ecp5-template
49 lines
871 B
Systemverilog
49 lines
871 B
Systemverilog
`timescale 1ns / 100ps // 1 ns time unit, 100 ps resolution
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module hub75e_tb;
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reg clk;
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reg write_trig;
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reg [1:0][7:0] rgb_row[128];
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wire [4:0] addr_out;
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wire [2:0] rgb0;
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wire [2:0] rgb1;
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wire display_clk;
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wire out_enable;
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wire latch;
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wire done;
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hub75e dut (
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.clk(clk),
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.write_trig(write_trig),
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.rgb_row(rgb_row),
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.addr(addr_out),
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.panel_rgb0(rgb0),
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.panel_rgb1(rgb1),
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.display_clk(display_clk),
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.out_enable(out_enable),
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.latch(latch),
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.done(done)
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);
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always #5 clk = !clk;
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initial begin
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$dumpfile("wave.vcd");
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$dumpvars(0, hub75e_tb);
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clk = 0;
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write_trig = 1;
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repeat (2) @(posedge clk);
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write_trig = 0;
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@(done);
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repeat (20) @(posedge clk);
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$finish();
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end
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initial begin
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repeat (100000) @(posedge clk);
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$finish();
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end
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endmodule
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