groovylight/verilog/tb/hub75e_tb.sv

`timescale 1ns / 100ps  // 1 ns time unit, 100 ps resolution
module hub75e_tb;

  reg clk;
  reg write_trig;

  reg [1:0][7:0] rgb_row[128];

  wire [4:0] addr_out;
  wire [2:0] rgb0;
  wire [2:0] rgb1;
  wire display_clk;
  wire out_enable;
  wire latch;
  wire done;


  hub75e dut (
      .clk(clk),
      .write_trig(write_trig),
      .rgb_row(rgb_row),
      .addr(addr_out),
      .panel_rgb0(rgb0),
      .panel_rgb1(rgb1),
      .display_clk(display_clk),
      .out_enable(out_enable),
      .latch(latch),
      .done(done)
  );

  always #5 clk = !clk;
  initial begin
    $dumpfile("wave.vcd");
    $dumpvars(0, hub75e_tb);
    clk = 0;
    write_trig = 1;
    repeat (2) @(posedge clk);
    write_trig = 0;

    @(done);
    repeat (20) @(posedge clk);
    $finish();
  end
  initial begin
    repeat (100000) @(posedge clk);
    $finish();
  end
endmodule