groovylight/verilog/tb/coordinator_tb.sv

`timescale 1ns / 100ps  // 1 ns time unit, 100 ps resolution

module coordinator_tb();
reg clk = 0;
coordinator dut(.clk(clk));
  always #8 clk = !clk;
  initial begin
    $dumpfile("coordinator.vcd");
    $dumpvars(0, coordinator_tb);
    repeat (100000) @(posedge clk);
    $finish;
  end
endmodule