generated from saji/ecp5-template
15 lines
301 B
Systemverilog
15 lines
301 B
Systemverilog
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`timescale 1ns / 100ps // 1 ns time unit, 100 ps resolution
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module coordinator_tb();
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reg clk = 0;
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coordinator dut(.clk(clk));
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always #8 clk = !clk;
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initial begin
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$dumpfile("coordinator.vcd");
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$dumpvars(0, coordinator_tb);
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repeat (10000) @(posedge clk);
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$finish;
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end
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endmodule
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