groovylight/verilog/bitslicer.sv

module bitslicer (
    input clk,
    input [23:0] rgb0,
    input [23:0] rgb1,
    input [7:0] pixnum,  // x-value of the pixels we are being fed.
    input start_write,
    output reg [5:0] bitplane_data,
    output [10:0] bitplane_addr,
    output reg bitplane_wren,
    output reg done
);

  reg [2:0] bitplane_bit = 0;
  assign bitplane_addr = {bitplane_bit, pixnum};
  assign bitplane_data = {
    rgb1[bitplane_bit],
    rgb1[bitplane_bit+8],
    rgb1[bitplane_bit+16],
    rgb0[bitplane_bit],
    rgb0[bitplane_bit+8],
    rgb0[bitplane_bit+16]
  };

  reg [3:0] state = StateInit;
  localparam integer StateInit = 0;
  localparam integer StateWriteout = 1;
  localparam integer StateDone = 2;


  always @(posedge clk) begin
    case (state)
      StateInit: begin
        bitplane_bit <= 0;
        done <= 0;
        bitplane_wren <= 0;
        if (start_write) begin
          state <= StateWriteout;
          bitplane_wren <= 1;
        end
      end
      StateWriteout: begin
        // bitplane_data <= {
        //   rgb[1][bitplane_bit],
        //   rgb[1][bitplane_bit+8],
        //   rgb[1][bitplane_bit+16],
        //   rgb[0][bitplane_bit],
        //   rgb[0][bitplane_bit+8],
        //   rgb[0][bitplane_bit+16]
        // };
        bitplane_bit <= bitplane_bit + 1;

        if (bitplane_bit == 7) begin
          state <= StateDone;
          bitplane_wren <= 0;
        end
      end
      StateDone: begin
        done <= 1;  // strobe
        state <= StateInit;
      end
      default: begin
        state <= StateInit;
      end
    endcase
  end
endmodule