2024-04-30 06:41:31 +00:00
|
|
|
module bitslicer (
|
|
|
|
input clk,
|
|
|
|
input [23:0] rgb[2],
|
2024-05-01 04:48:10 +00:00
|
|
|
input [8:0] pixnum, // x-value of the pixels we are being fed.
|
2024-04-30 06:41:31 +00:00
|
|
|
input start_write,
|
|
|
|
output reg [5:0] bitplane_data,
|
|
|
|
output [10:0] bitplane_addr,
|
|
|
|
output reg bitplane_wren,
|
|
|
|
output reg done
|
|
|
|
);
|
|
|
|
|
2024-05-01 04:48:10 +00:00
|
|
|
reg [2:0] bitplane_bit = 0;
|
2024-04-30 06:41:31 +00:00
|
|
|
assign bitplane_addr = (pixnum << 3) + bitplane_bit;
|
2024-05-01 04:48:10 +00:00
|
|
|
assign bitplane_data = {
|
|
|
|
rgb[1][bitplane_bit],
|
|
|
|
rgb[1][bitplane_bit+8],
|
|
|
|
rgb[1][bitplane_bit+16],
|
|
|
|
rgb[0][bitplane_bit],
|
|
|
|
rgb[0][bitplane_bit+8],
|
|
|
|
rgb[0][bitplane_bit+16]
|
|
|
|
};
|
2024-04-30 06:41:31 +00:00
|
|
|
|
|
|
|
reg [3:0] state = StateInit;
|
|
|
|
localparam integer StateInit = 0;
|
|
|
|
localparam integer StateWriteout = 1;
|
|
|
|
localparam integer StateDone = 2;
|
|
|
|
|
|
|
|
|
|
|
|
always @(posedge clk) begin
|
|
|
|
case (state)
|
|
|
|
StateInit: begin
|
|
|
|
bitplane_bit <= 0;
|
|
|
|
done <= 0;
|
|
|
|
bitplane_wren <= 0;
|
|
|
|
if (start_write) begin
|
|
|
|
state <= StateWriteout;
|
2024-05-01 04:48:10 +00:00
|
|
|
bitplane_wren <= 1;
|
2024-04-30 06:41:31 +00:00
|
|
|
end
|
|
|
|
end
|
|
|
|
StateWriteout: begin
|
2024-05-01 04:48:10 +00:00
|
|
|
// bitplane_data <= {
|
|
|
|
// rgb[1][bitplane_bit],
|
|
|
|
// rgb[1][bitplane_bit+8],
|
|
|
|
// rgb[1][bitplane_bit+16],
|
|
|
|
// rgb[0][bitplane_bit],
|
|
|
|
// rgb[0][bitplane_bit+8],
|
|
|
|
// rgb[0][bitplane_bit+16]
|
|
|
|
// };
|
2024-04-30 06:41:31 +00:00
|
|
|
bitplane_bit <= bitplane_bit + 1;
|
|
|
|
|
|
|
|
if (bitplane_bit == 7) begin
|
|
|
|
state <= StateDone;
|
2024-05-01 04:48:10 +00:00
|
|
|
bitplane_wren <= 0;
|
2024-04-30 06:41:31 +00:00
|
|
|
end
|
|
|
|
end
|
|
|
|
StateDone: begin
|
2024-05-01 04:48:10 +00:00
|
|
|
done <= 1; // strobe
|
2024-04-30 06:41:31 +00:00
|
|
|
state <= StateInit;
|
|
|
|
end
|
|
|
|
default: begin
|
|
|
|
state <= StateInit;
|
|
|
|
end
|
|
|
|
endcase
|
|
|
|
end
|
|
|
|
endmodule
|